1 /*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch_helpers.h>
8 #include <arm_gic.h>
9 #include <assert.h>
10 #include <bl_common.h>
11 #include <debug.h>
12 #include <mmio.h>
13 #include <platform.h>
14 #include <platform_def.h>
15 #include <xlat_tables.h>
16
17 #include "../hikey960_def.h"
18 #include "../hikey960_private.h"
19
20 #define MAP_DDR MAP_REGION_FLAT(DDR_BASE, \
21 DDR_SIZE, \
22 MT_MEMORY | MT_RW | MT_NS)
23
24 #define MAP_DEVICE MAP_REGION_FLAT(DEVICE_BASE, \
25 DEVICE_SIZE, \
26 MT_DEVICE | MT_RW | MT_SECURE)
27
28 #define MAP_BL1_RW MAP_REGION_FLAT(BL1_RW_BASE, \
29 BL1_RW_LIMIT - BL1_RW_BASE, \
30 MT_MEMORY | MT_RW | MT_NS)
31
32 #define MAP_UFS_DATA MAP_REGION_FLAT(HIKEY960_UFS_DATA_BASE, \
33 HIKEY960_UFS_DATA_SIZE, \
34 MT_MEMORY | MT_RW | MT_NS)
35
36 #define MAP_UFS_DESC MAP_REGION_FLAT(HIKEY960_UFS_DESC_BASE, \
37 HIKEY960_UFS_DESC_SIZE, \
38 MT_MEMORY | MT_RW | MT_NS)
39
40 #define MAP_TSP_MEM MAP_REGION_FLAT(TSP_SEC_MEM_BASE, \
41 TSP_SEC_MEM_SIZE, \
42 MT_MEMORY | MT_RW | MT_SECURE)
43
44 #if LOAD_IMAGE_V2
45 #ifdef SPD_opteed
46 #define MAP_OPTEE_PAGEABLE MAP_REGION_FLAT( \
47 HIKEY960_OPTEE_PAGEABLE_LOAD_BASE, \
48 HIKEY960_OPTEE_PAGEABLE_LOAD_SIZE, \
49 MT_MEMORY | MT_RW | MT_SECURE)
50 #endif
51 #endif
52
53 /*
54 * Table of regions for different BL stages to map using the MMU.
55 * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
56 * hikey960_init_mmu_elx() will give the available subset of that,
57 */
58 #ifdef IMAGE_BL1
59 static const mmap_region_t hikey960_mmap[] = {
60 MAP_UFS_DATA,
61 MAP_BL1_RW,
62 MAP_UFS_DESC,
63 MAP_DEVICE,
64 {0}
65 };
66 #endif
67
68 #ifdef IMAGE_BL2
69 static const mmap_region_t hikey960_mmap[] = {
70 MAP_DDR,
71 MAP_DEVICE,
72 MAP_TSP_MEM,
73 #if LOAD_IMAGE_V2
74 #ifdef SPD_opteed
75 MAP_OPTEE_PAGEABLE,
76 #endif
77 #endif
78 {0}
79 };
80 #endif
81
82 #ifdef IMAGE_BL31
83 static const mmap_region_t hikey960_mmap[] = {
84 MAP_DEVICE,
85 MAP_TSP_MEM,
86 {0}
87 };
88 #endif
89
90 #ifdef IMAGE_BL32
91 static const mmap_region_t hikey960_mmap[] = {
92 MAP_DEVICE,
93 MAP_DDR,
94 {0}
95 };
96 #endif
97
98 /*
99 * Macro generating the code for the function setting up the pagetables as per
100 * the platform memory map & initialize the mmu, for the given exception level
101 */
102 #define HIKEY960_CONFIGURE_MMU_EL(_el) \
103 void hikey960_init_mmu_el##_el(unsigned long total_base, \
104 unsigned long total_size, \
105 unsigned long ro_start, \
106 unsigned long ro_limit, \
107 unsigned long coh_start, \
108 unsigned long coh_limit) \
109 { \
110 mmap_add_region(total_base, total_base, \
111 total_size, \
112 MT_MEMORY | MT_RW | MT_SECURE); \
113 mmap_add_region(ro_start, ro_start, \
114 ro_limit - ro_start, \
115 MT_MEMORY | MT_RO | MT_SECURE); \
116 mmap_add_region(coh_start, coh_start, \
117 coh_limit - coh_start, \
118 MT_DEVICE | MT_RW | MT_SECURE); \
119 mmap_add(hikey960_mmap); \
120 init_xlat_tables(); \
121 \
122 enable_mmu_el##_el(0); \
123 }
124
125 /* Define EL1 and EL3 variants of the function initialising the MMU */
126 HIKEY960_CONFIGURE_MMU_EL(1)
127 HIKEY960_CONFIGURE_MMU_EL(3)
128
plat_get_ns_image_entrypoint(void)129 unsigned long plat_get_ns_image_entrypoint(void)
130 {
131 return NS_BL1U_BASE;
132 }
133
plat_get_syscnt_freq2(void)134 unsigned int plat_get_syscnt_freq2(void)
135 {
136 return 1920000;
137 }
138