1 /*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch_helpers.h>
8 #include <arm_gic.h>
9 #include <assert.h>
10 #include <bl_common.h>
11 #include <cci.h>
12 #include <console.h>
13 #include <debug.h>
14 #include <errno.h>
15 #include <generic_delay_timer.h>
16 #include <gicv2.h>
17 #include <hi3660.h>
18 #include <hisi_ipc.h>
19 #include <platform_def.h>
20
21 #include "hikey960_def.h"
22 #include "hikey960_private.h"
23
24 /*
25 * The next 2 constants identify the extents of the code & RO data region.
26 * These addresses are used by the MMU setup code and therefore they must be
27 * page-aligned. It is the responsibility of the linker script to ensure that
28 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
29 */
30 #define BL31_RO_BASE (unsigned long)(&__RO_START__)
31 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
32
33 /*
34 * The next 2 constants identify the extents of the coherent memory region.
35 * These addresses are used by the MMU setup code and therefore they must be
36 * page-aligned. It is the responsibility of the linker script to ensure that
37 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
38 * page-aligned addresses.
39 */
40 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
41 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
42
43 static entry_point_info_t bl32_ep_info;
44 static entry_point_info_t bl33_ep_info;
45
46 /******************************************************************************
47 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
48 * interrupts.
49 *****************************************************************************/
50 const unsigned int g0_interrupt_array[] = {
51 IRQ_SEC_PHY_TIMER,
52 IRQ_SEC_SGI_0
53 };
54
55 const gicv2_driver_data_t hikey960_gic_data = {
56 .gicd_base = GICD_REG_BASE,
57 .gicc_base = GICC_REG_BASE,
58 .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
59 .g0_interrupt_array = g0_interrupt_array,
60 };
61
62 static const int cci_map[] = {
63 CCI400_SL_IFACE3_CLUSTER_IX,
64 CCI400_SL_IFACE4_CLUSTER_IX
65 };
66
bl31_plat_get_next_image_ep_info(uint32_t type)67 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
68 {
69 entry_point_info_t *next_image_info;
70
71 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
72
73 /* None of the images on this platform can have 0x0 as the entrypoint */
74 if (next_image_info->pc)
75 return next_image_info;
76 return NULL;
77 }
78
79 #if LOAD_IMAGE_V2
bl31_early_platform_setup(void * from_bl2,void * plat_params_from_bl2)80 void bl31_early_platform_setup(void *from_bl2,
81 void *plat_params_from_bl2)
82 #else
83 void bl31_early_platform_setup(bl31_params_t *from_bl2,
84 void *plat_params_from_bl2)
85 #endif
86 {
87 unsigned int id, uart_base;
88
89 generic_delay_timer_init();
90 hikey960_read_boardid(&id);
91 if (id == 5300)
92 uart_base = PL011_UART5_BASE;
93 else
94 uart_base = PL011_UART6_BASE;
95
96 /* Initialize the console to provide early debug support */
97 console_init(uart_base, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
98
99 /* Initialize CCI driver */
100 cci_init(CCI400_REG_BASE, cci_map, ARRAY_SIZE(cci_map));
101 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
102
103 #if LOAD_IMAGE_V2
104 /*
105 * Check params passed from BL2 should not be NULL,
106 */
107 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
108 assert(params_from_bl2 != NULL);
109 assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
110 assert(params_from_bl2->h.version >= VERSION_2);
111
112 bl_params_node_t *bl_params = params_from_bl2->head;
113
114 /*
115 * Copy BL33 and BL32 (if present), entry point information.
116 * They are stored in Secure RAM, in BL2's address space.
117 */
118 while (bl_params) {
119 if (bl_params->image_id == BL32_IMAGE_ID)
120 bl32_ep_info = *bl_params->ep_info;
121
122 if (bl_params->image_id == BL33_IMAGE_ID)
123 bl33_ep_info = *bl_params->ep_info;
124
125 bl_params = bl_params->next_params_info;
126 }
127
128 if (bl33_ep_info.pc == 0)
129 panic();
130
131 #else /* LOAD_IMAGE_V2 */
132
133 /*
134 * Check params passed from BL2 should not be NULL,
135 */
136 assert(from_bl2 != NULL);
137 assert(from_bl2->h.type == PARAM_BL31);
138 assert(from_bl2->h.version >= VERSION_1);
139
140 /*
141 * Copy BL3-2 and BL3-3 entry point information.
142 * They are stored in Secure RAM, in BL2's address space.
143 */
144 bl32_ep_info = *from_bl2->bl32_ep_info;
145 bl33_ep_info = *from_bl2->bl33_ep_info;
146 #endif /* LOAD_IMAGE_V2 */
147 }
148
bl31_plat_arch_setup(void)149 void bl31_plat_arch_setup(void)
150 {
151 hikey960_init_mmu_el3(BL31_BASE,
152 BL31_LIMIT - BL31_BASE,
153 BL31_RO_BASE,
154 BL31_RO_LIMIT,
155 BL31_COHERENT_RAM_BASE,
156 BL31_COHERENT_RAM_LIMIT);
157 }
158
bl31_platform_setup(void)159 void bl31_platform_setup(void)
160 {
161 /* Initialize the GIC driver, cpu and distributor interfaces */
162 gicv2_driver_init(&hikey960_gic_data);
163 gicv2_distif_init();
164 gicv2_pcpu_distif_init();
165 gicv2_cpuif_enable();
166
167 hisi_ipc_init();
168 }
169
bl31_plat_runtime_setup(void)170 void bl31_plat_runtime_setup(void)
171 {
172 }
173