1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <arch.h> 11 #include <common_def.h> 12 #include <gic_common.h> 13 #include <interrupt_props.h> 14 #include <tbbr/tbbr_img_def.h> 15 #include "hi3798cv200.h" 16 #include "poplar_layout.h" /* BL memory region sizes, etc */ 17 18 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 19 #define PLATFORM_LINKER_ARCH aarch64 20 21 #define PLAT_ARM_CRASH_UART_BASE PL011_UART0_BASE 22 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PL011_UART0_CLK_IN_HZ 23 #define ARM_CONSOLE_BAUDRATE PL011_BAUDRATE 24 25 /* Generic platform constants */ 26 #define PLATFORM_STACK_SIZE (0x800) 27 28 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 29 #define BOOT_EMMC_NAME "l-loader.bin" 30 31 #define PLATFORM_CACHE_LINE_SIZE (64) 32 #define PLATFORM_CLUSTER_COUNT (1) 33 #define PLATFORM_CORE_COUNT (4) 34 #define PLATFORM_MAX_CPUS_PER_CLUSTER (4) 35 36 /* IO framework user */ 37 #define MAX_IO_DEVICES (4) 38 #define MAX_IO_HANDLES (4) 39 #define MAX_IO_BLOCK_DEVICES (2) 40 41 /* Memory map related constants */ 42 #define DDR_BASE (0x00000000) 43 #define DDR_SIZE (0x40000000) 44 45 #define DEVICE_BASE (0xF0000000) 46 #define DEVICE_SIZE (0x0F000000) 47 48 #define TEE_SEC_MEM_BASE (0x70000000) 49 #define TEE_SEC_MEM_SIZE (0x10000000) 50 51 #define BL_MEM_BASE (BL1_RO_BASE) 52 #define BL_MEM_LIMIT (BL31_LIMIT) 53 #define BL_MEM_SIZE (BL_MEM_LIMIT - BL_MEM_BASE) 54 55 #define PLAT_ARM_NS_IMAGE_OFFSET 0x37000000 56 57 /* Page table and MMU setup constants */ 58 #define ADDR_SPACE_SIZE (1ull << 32) 59 #define MAX_XLAT_TABLES (4) 60 #define MAX_MMAP_REGIONS (16) 61 62 #define CACHE_WRITEBACK_SHIFT (6) 63 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 64 65 /* Power states */ 66 #define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL1) 67 #define PLAT_MAX_OFF_STATE 2 68 #define PLAT_MAX_RET_STATE 1 69 70 /* Interrupt controller */ 71 #define PLAT_ARM_GICD_BASE GICD_BASE 72 #define PLAT_ARM_GICC_BASE GICC_BASE 73 74 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 75 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 76 GIC_INTR_CFG_LEVEL), \ 77 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 78 GIC_INTR_CFG_LEVEL), \ 79 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 80 GIC_INTR_CFG_LEVEL), \ 81 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 82 GIC_INTR_CFG_LEVEL), \ 83 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 84 GIC_INTR_CFG_LEVEL), \ 85 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 86 GIC_INTR_CFG_LEVEL), \ 87 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 88 GIC_INTR_CFG_LEVEL), \ 89 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 90 GIC_INTR_CFG_LEVEL), \ 91 INTR_PROP_DESC(HISI_IRQ_SEC_TIMER0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 92 GIC_INTR_CFG_LEVEL), \ 93 INTR_PROP_DESC(HISI_IRQ_SEC_TIMER1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 94 GIC_INTR_CFG_LEVEL), \ 95 INTR_PROP_DESC(HISI_IRQ_SEC_TIMER2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 96 GIC_INTR_CFG_LEVEL), \ 97 INTR_PROP_DESC(HISI_IRQ_SEC_TIMER3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 98 GIC_INTR_CFG_LEVEL), \ 99 INTR_PROP_DESC(HISI_IRQ_SEC_AXI, GIC_HIGHEST_SEC_PRIORITY, grp, \ 100 GIC_INTR_CFG_LEVEL) 101 102 #define PLAT_ARM_G0_IRQ_PROPS(grp) 103 104 #endif /* __PLATFORM_DEF_H__ */ 105