1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __TEGRA_DEF_H__ 8 #define __TEGRA_DEF_H__ 9 10 #include <utils_def.h> 11 12 /******************************************************************************* 13 * Power down state IDs 14 ******************************************************************************/ 15 #define PSTATE_ID_CORE_POWERDN U(7) 16 #define PSTATE_ID_CLUSTER_IDLE U(16) 17 #define PSTATE_ID_CLUSTER_POWERDN U(17) 18 #define PSTATE_ID_SOC_POWERDN U(27) 19 20 /******************************************************************************* 21 * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` 22 * call as the `state-id` field in the 'power state' parameter. 23 ******************************************************************************/ 24 #define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN 25 26 /******************************************************************************* 27 * Platform power states (used by PSCI framework) 28 * 29 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 30 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 31 ******************************************************************************/ 32 #define PLAT_MAX_RET_STATE U(1) 33 #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1)) 34 35 /******************************************************************************* 36 * GIC memory map 37 ******************************************************************************/ 38 #define TEGRA_GICD_BASE U(0x50041000) 39 #define TEGRA_GICC_BASE U(0x50042000) 40 41 /******************************************************************************* 42 * Tegra Memory Select Switch Controller constants 43 ******************************************************************************/ 44 #define TEGRA_MSELECT_BASE U(0x50060000) 45 46 #define MSELECT_CONFIG U(0x0) 47 #define ENABLE_WRAP_INCR_MASTER2_BIT (U(1) << U(29)) 48 #define ENABLE_WRAP_INCR_MASTER1_BIT (U(1) << U(28)) 49 #define ENABLE_WRAP_INCR_MASTER0_BIT (U(1) << U(27)) 50 #define UNSUPPORTED_TX_ERR_MASTER2_BIT (U(1) << U(25)) 51 #define UNSUPPORTED_TX_ERR_MASTER1_BIT (U(1) << U(24)) 52 #define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \ 53 UNSUPPORTED_TX_ERR_MASTER1_BIT) 54 #define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \ 55 ENABLE_WRAP_INCR_MASTER1_BIT | \ 56 ENABLE_WRAP_INCR_MASTER0_BIT) 57 58 /******************************************************************************* 59 * Tegra micro-seconds timer constants 60 ******************************************************************************/ 61 #define TEGRA_TMRUS_BASE U(0x60005010) 62 #define TEGRA_TMRUS_SIZE U(0x1000) 63 64 /******************************************************************************* 65 * Tegra Clock and Reset Controller constants 66 ******************************************************************************/ 67 #define TEGRA_CAR_RESET_BASE U(0x60006000) 68 #define TEGRA_GPU_RESET_REG_OFFSET U(0x28C) 69 #define GPU_RESET_BIT (U(1) << 24) 70 71 /******************************************************************************* 72 * Tegra Flow Controller constants 73 ******************************************************************************/ 74 #define TEGRA_FLOWCTRL_BASE U(0x60007000) 75 76 /******************************************************************************* 77 * Tegra Secure Boot Controller constants 78 ******************************************************************************/ 79 #define TEGRA_SB_BASE U(0x6000C200) 80 81 /******************************************************************************* 82 * Tegra Exception Vectors constants 83 ******************************************************************************/ 84 #define TEGRA_EVP_BASE U(0x6000F000) 85 86 /******************************************************************************* 87 * Tegra Miscellaneous register constants 88 ******************************************************************************/ 89 #define TEGRA_MISC_BASE U(0x70000000) 90 #define HARDWARE_REVISION_OFFSET U(0x804) 91 92 /******************************************************************************* 93 * Tegra UART controller base addresses 94 ******************************************************************************/ 95 #define TEGRA_UARTA_BASE U(0x70006000) 96 #define TEGRA_UARTB_BASE U(0x70006040) 97 #define TEGRA_UARTC_BASE U(0x70006200) 98 #define TEGRA_UARTD_BASE U(0x70006300) 99 #define TEGRA_UARTE_BASE U(0x70006400) 100 101 /******************************************************************************* 102 * Tegra Power Mgmt Controller constants 103 ******************************************************************************/ 104 #define TEGRA_PMC_BASE U(0x7000E400) 105 106 /******************************************************************************* 107 * Tegra Memory Controller constants 108 ******************************************************************************/ 109 #define TEGRA_MC_BASE U(0x70019000) 110 111 /* TZDRAM carveout configuration registers */ 112 #define MC_SECURITY_CFG0_0 U(0x70) 113 #define MC_SECURITY_CFG1_0 U(0x74) 114 #define MC_SECURITY_CFG3_0 U(0x9BC) 115 116 /* Video Memory carveout configuration registers */ 117 #define MC_VIDEO_PROTECT_BASE_HI U(0x978) 118 #define MC_VIDEO_PROTECT_BASE_LO U(0x648) 119 #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) 120 121 /******************************************************************************* 122 * Tegra TZRAM constants 123 ******************************************************************************/ 124 #define TEGRA_TZRAM_BASE U(0x7C010000) 125 #define TEGRA_TZRAM_SIZE U(0x10000) 126 127 #endif /* __TEGRA_DEF_H__ */ 128