1 /*
2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch_helpers.h>
8 #include <bl_common.h>
9 #include <tegra_def.h>
10 #include <tegra_private.h>
11 #include <xlat_tables.h>
12
13 /*******************************************************************************
14 * The Tegra power domain tree has a single system level power domain i.e. a
15 * single root node. The first entry in the power domain descriptor specifies
16 * the number of power domains at the highest power level.
17 *******************************************************************************
18 */
19 const unsigned char tegra_power_domain_tree_desc[] = {
20 /* No of root nodes */
21 1,
22 /* No of clusters */
23 PLATFORM_CLUSTER_COUNT,
24 /* No of CPU cores */
25 PLATFORM_CORE_COUNT,
26 };
27
28 /* sets of MMIO ranges setup */
29 #define MMIO_RANGE_0_ADDR 0x50000000
30 #define MMIO_RANGE_1_ADDR 0x60000000
31 #define MMIO_RANGE_2_ADDR 0x70000000
32 #define MMIO_RANGE_SIZE 0x200000
33
34 /*
35 * Table of regions to map using the MMU.
36 */
37 static const mmap_region_t tegra_mmap[] = {
38 MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE,
39 MT_DEVICE | MT_RW | MT_SECURE),
40 MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE,
41 MT_DEVICE | MT_RW | MT_SECURE),
42 MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE,
43 MT_DEVICE | MT_RW | MT_SECURE),
44 {0}
45 };
46
47 /*******************************************************************************
48 * Set up the pagetables as per the platform memory map & initialize the MMU
49 ******************************************************************************/
plat_get_mmio_map(void)50 const mmap_region_t *plat_get_mmio_map(void)
51 {
52 /* MMIO space */
53 return tegra_mmap;
54 }
55
plat_get_syscnt_freq2(void)56 unsigned int plat_get_syscnt_freq2(void)
57 {
58 return 12000000;
59 }
60
61 /*******************************************************************************
62 * Maximum supported UART controllers
63 ******************************************************************************/
64 #define TEGRA132_MAX_UART_PORTS 5
65
66 /*******************************************************************************
67 * This variable holds the UART port base addresses
68 ******************************************************************************/
69 static uint32_t tegra132_uart_addresses[TEGRA132_MAX_UART_PORTS + 1] = {
70 0, /* undefined - treated as an error case */
71 TEGRA_UARTA_BASE,
72 TEGRA_UARTB_BASE,
73 TEGRA_UARTC_BASE,
74 TEGRA_UARTD_BASE,
75 TEGRA_UARTE_BASE,
76 };
77
78 /*******************************************************************************
79 * Retrieve the UART controller base to be used as the console
80 ******************************************************************************/
plat_get_console_from_id(int id)81 uint32_t plat_get_console_from_id(int id)
82 {
83 if (id > TEGRA132_MAX_UART_PORTS)
84 return 0;
85
86 return tegra132_uart_addresses[id];
87 }
88
89 /*******************************************************************************
90 * Initialize the GIC and SGIs
91 ******************************************************************************/
plat_gic_setup(void)92 void plat_gic_setup(void)
93 {
94 tegra_gic_setup(NULL, 0);
95 }
96