1 /* 2 * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <arch.h> 11 #include <gic_common.h> 12 #include <interrupt_props.h> 13 #include "../zynqmp_def.h" 14 15 /******************************************************************************* 16 * Generic platform constants 17 ******************************************************************************/ 18 19 /* Size of cacheable stacks */ 20 #define PLATFORM_STACK_SIZE 0x440 21 22 #define PLATFORM_CORE_COUNT 4 23 #define PLAT_NUM_POWER_DOMAINS 5 24 #define PLAT_MAX_PWR_LVL 1 25 #define PLAT_MAX_RET_STATE 1 26 #define PLAT_MAX_OFF_STATE 2 27 28 /******************************************************************************* 29 * BL31 specific defines. 30 ******************************************************************************/ 31 /* 32 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 33 * present). BL31_BASE is calculated using the current BL31 debug size plus a 34 * little space for growth. 35 */ 36 #ifndef ZYNQMP_ATF_MEM_BASE 37 # define BL31_BASE 0xfffea000 38 # define BL31_LIMIT 0xffffffff 39 #else 40 # define BL31_BASE (ZYNQMP_ATF_MEM_BASE) 41 # define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE - 1) 42 # ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE 43 # define BL31_PROGBITS_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_PROGBITS_SIZE - 1) 44 # endif 45 #endif 46 47 /******************************************************************************* 48 * BL32 specific defines. 49 ******************************************************************************/ 50 #ifndef ZYNQMP_BL32_MEM_BASE 51 # define BL32_BASE 0x60000000 52 # define BL32_LIMIT 0x7fffffff 53 #else 54 # define BL32_BASE (ZYNQMP_BL32_MEM_BASE) 55 # define BL32_LIMIT (ZYNQMP_BL32_MEM_BASE + ZYNQMP_BL32_MEM_SIZE - 1) 56 #endif 57 58 /******************************************************************************* 59 * BL33 specific defines. 60 ******************************************************************************/ 61 #ifndef PRELOADED_BL33_BASE 62 # define PLAT_ARM_NS_IMAGE_OFFSET 0x8000000 63 #else 64 # define PLAT_ARM_NS_IMAGE_OFFSET PRELOADED_BL33_BASE 65 #endif 66 67 /******************************************************************************* 68 * TSP specific defines. 69 ******************************************************************************/ 70 #define TSP_SEC_MEM_BASE BL32_BASE 71 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) 72 73 /* ID of the secure physical generic timer interrupt used by the TSP */ 74 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 75 76 /******************************************************************************* 77 * Platform specific page table and MMU setup constants 78 ******************************************************************************/ 79 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 80 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 81 #define MAX_MMAP_REGIONS 7 82 #define MAX_XLAT_TABLES 5 83 84 #define CACHE_WRITEBACK_SHIFT 6 85 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 86 87 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 88 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 89 /* 90 * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 91 * terminology. On a GICv2 system or mode, the lists will be merged and treated 92 * as Group 0 interrupts. 93 */ 94 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 95 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 96 GIC_INTR_CFG_LEVEL), \ 97 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 98 GIC_INTR_CFG_EDGE), \ 99 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 100 GIC_INTR_CFG_EDGE), \ 101 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 102 GIC_INTR_CFG_EDGE), \ 103 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 104 GIC_INTR_CFG_EDGE), \ 105 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 106 GIC_INTR_CFG_EDGE), \ 107 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 108 GIC_INTR_CFG_EDGE), \ 109 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 110 GIC_INTR_CFG_EDGE), \ 111 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 112 GIC_INTR_CFG_EDGE) 113 114 #define PLAT_ARM_G0_IRQ_PROPS(grp) 115 116 #endif /* __PLATFORM_DEF_H__ */ 117