1#------------------------------------------------------------------------------ 2# 3# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> 4# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. 5# Copyright (c) 2016, Linaro Limited. All rights reserved. 6# 7# This program and the accompanying materials 8# are licensed and made available under the terms and conditions of the BSD License 9# which accompanies this distribution. The full text of the license may be found at 10# http://opensource.org/licenses/bsd-license.php 11# 12# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 13# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 14# 15#------------------------------------------------------------------------------ 16 17#include <AsmMacroIoLibV8.h> 18 19.set MPIDR_U_BIT, (30) 20.set MPIDR_U_MASK, (1 << MPIDR_U_BIT) 21 22// DAIF bit definitions for writing through msr daifclr/sr daifset 23.set DAIF_WR_FIQ_BIT, (1 << 0) 24.set DAIF_WR_IRQ_BIT, (1 << 1) 25.set DAIF_WR_ABORT_BIT, (1 << 2) 26.set DAIF_WR_DEBUG_BIT, (1 << 3) 27.set DAIF_WR_INT_BITS, (DAIF_WR_FIQ_BIT | DAIF_WR_IRQ_BIT) 28.set DAIF_WR_ALL, (DAIF_WR_DEBUG_BIT | DAIF_WR_ABORT_BIT | DAIF_WR_INT_BITS) 29 30 31ASM_FUNC(ArmIsMpCore) 32 mrs x0, mpidr_el1 // Read EL1 Mutliprocessor Affinty Reg (MPIDR) 33 and x0, x0, #MPIDR_U_MASK // U Bit clear, the processor is part of a multiprocessor system 34 lsr x0, x0, #MPIDR_U_BIT 35 eor x0, x0, #1 36 ret 37 38 39ASM_FUNC(ArmEnableAsynchronousAbort) 40 msr daifclr, #DAIF_WR_ABORT_BIT 41 isb 42 ret 43 44 45ASM_FUNC(ArmDisableAsynchronousAbort) 46 msr daifset, #DAIF_WR_ABORT_BIT 47 isb 48 ret 49 50 51ASM_FUNC(ArmEnableIrq) 52 msr daifclr, #DAIF_WR_IRQ_BIT 53 isb 54 ret 55 56 57ASM_FUNC(ArmDisableIrq) 58 msr daifset, #DAIF_WR_IRQ_BIT 59 isb 60 ret 61 62 63ASM_FUNC(ArmEnableFiq) 64 msr daifclr, #DAIF_WR_FIQ_BIT 65 isb 66 ret 67 68 69ASM_FUNC(ArmDisableFiq) 70 msr daifset, #DAIF_WR_FIQ_BIT 71 isb 72 ret 73 74 75ASM_FUNC(ArmEnableInterrupts) 76 msr daifclr, #DAIF_WR_INT_BITS 77 isb 78 ret 79 80 81ASM_FUNC(ArmDisableInterrupts) 82 msr daifset, #DAIF_WR_INT_BITS 83 isb 84 ret 85 86 87ASM_FUNC(ArmDisableAllExceptions) 88 msr daifset, #DAIF_WR_ALL 89 isb 90 ret 91 92 93// UINT32 94// ReadCCSIDR ( 95// IN UINT32 CSSELR 96// ) 97ASM_FUNC(ReadCCSIDR) 98 msr csselr_el1, x0 // Write Cache Size Selection Register (CSSELR) 99 isb 100 mrs x0, ccsidr_el1 // Read current Cache Size ID Register (CCSIDR) 101 ret 102 103 104// UINT32 105// ReadCLIDR ( 106// IN UINT32 CSSELR 107// ) 108ASM_FUNC(ReadCLIDR) 109 mrs x0, clidr_el1 // Read Cache Level ID Register 110 ret 111 112ASM_FUNCTION_REMOVE_IF_UNREFERENCED 113