1//------------------------------------------------------------------------------ 2// 3// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> 4// Copyright (c) 2011 - 2016, ARM Limited. All rights reserved. 5// 6// This program and the accompanying materials 7// are licensed and made available under the terms and conditions of the BSD License 8// which accompanies this distribution. The full text of the license may be found at 9// http://opensource.org/licenses/bsd-license.php 10// 11// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13// 14//------------------------------------------------------------------------------ 15 16 INCLUDE AsmMacroIoLib.inc 17 18 19 INCLUDE AsmMacroExport.inc 20 21 RVCT_ASM_EXPORT ArmReadMidr 22 mrc p15,0,R0,c0,c0,0 23 bx LR 24 25 RVCT_ASM_EXPORT ArmCacheInfo 26 mrc p15,0,R0,c0,c0,1 27 bx LR 28 29 RVCT_ASM_EXPORT ArmGetInterruptState 30 mrs R0,CPSR 31 tst R0,#0x80 // Check if IRQ is enabled. 32 moveq R0,#1 33 movne R0,#0 34 bx LR 35 36 RVCT_ASM_EXPORT ArmGetFiqState 37 mrs R0,CPSR 38 tst R0,#0x40 // Check if FIQ is enabled. 39 moveq R0,#1 40 movne R0,#0 41 bx LR 42 43 RVCT_ASM_EXPORT ArmSetDomainAccessControl 44 mcr p15,0,r0,c3,c0,0 45 bx lr 46 47 RVCT_ASM_EXPORT CPSRMaskInsert 48 stmfd sp!, {r4-r12, lr} // save all the banked registers 49 mov r3, sp // copy the stack pointer into a non-banked register 50 mrs r2, cpsr // read the cpsr 51 bic r2, r2, r0 // clear mask in the cpsr 52 and r1, r1, r0 // clear bits outside the mask in the input 53 orr r2, r2, r1 // set field 54 msr cpsr_cxsf, r2 // write back cpsr (may have caused a mode switch) 55 isb 56 mov sp, r3 // restore stack pointer 57 ldmfd sp!, {r4-r12, lr} // restore registers 58 bx lr // return (hopefully thumb-safe!) // return (hopefully thumb-safe!) 59 60 RVCT_ASM_EXPORT CPSRRead 61 mrs r0, cpsr 62 bx lr 63 64 RVCT_ASM_EXPORT ArmReadCpacr 65 mrc p15, 0, r0, c1, c0, 2 66 bx lr 67 68 RVCT_ASM_EXPORT ArmWriteCpacr 69 mcr p15, 0, r0, c1, c0, 2 70 isb 71 bx lr 72 73 RVCT_ASM_EXPORT ArmWriteAuxCr 74 mcr p15, 0, r0, c1, c0, 1 75 bx lr 76 77 RVCT_ASM_EXPORT ArmReadAuxCr 78 mrc p15, 0, r0, c1, c0, 1 79 bx lr 80 81 RVCT_ASM_EXPORT ArmSetTTBR0 82 mcr p15,0,r0,c2,c0,0 83 isb 84 bx lr 85 86 RVCT_ASM_EXPORT ArmSetTTBCR 87 mcr p15, 0, r0, c2, c0, 2 88 isb 89 bx lr 90 91 RVCT_ASM_EXPORT ArmGetTTBR0BaseAddress 92 mrc p15,0,r0,c2,c0,0 93 MOV32 r1, 0xFFFFC000 94 and r0, r0, r1 95 isb 96 bx lr 97 98// 99//VOID 100//ArmUpdateTranslationTableEntry ( 101// IN VOID *TranslationTableEntry // R0 102// IN VOID *MVA // R1 103// ); 104 RVCT_ASM_EXPORT ArmUpdateTranslationTableEntry 105 mcr p15,0,R0,c7,c14,1 // DCCIMVAC Clean data cache by MVA 106 dsb 107 mcr p15,0,R1,c8,c7,1 // TLBIMVA TLB Invalidate MVA 108 mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp 109 dsb 110 isb 111 bx lr 112 113 RVCT_ASM_EXPORT ArmInvalidateTlb 114 mov r0,#0 115 mcr p15,0,r0,c8,c7,0 116 mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp 117 dsb 118 isb 119 bx lr 120 121 RVCT_ASM_EXPORT ArmReadScr 122 mrc p15, 0, r0, c1, c1, 0 123 bx lr 124 125 RVCT_ASM_EXPORT ArmWriteScr 126 mcr p15, 0, r0, c1, c1, 0 127 isb 128 bx lr 129 130 RVCT_ASM_EXPORT ArmReadHVBar 131 mrc p15, 4, r0, c12, c0, 0 132 bx lr 133 134 RVCT_ASM_EXPORT ArmWriteHVBar 135 mcr p15, 4, r0, c12, c0, 0 136 bx lr 137 138 RVCT_ASM_EXPORT ArmReadMVBar 139 mrc p15, 0, r0, c12, c0, 1 140 bx lr 141 142 RVCT_ASM_EXPORT ArmWriteMVBar 143 mcr p15, 0, r0, c12, c0, 1 144 bx lr 145 146 RVCT_ASM_EXPORT ArmCallWFE 147 wfe 148 bx lr 149 150 RVCT_ASM_EXPORT ArmCallSEV 151 sev 152 bx lr 153 154 RVCT_ASM_EXPORT ArmReadSctlr 155 mrc p15, 0, r0, c1, c0, 0 // Read SCTLR into R0 (Read control register configuration data) 156 bx lr 157 158 159 RVCT_ASM_EXPORT ArmReadCpuActlr 160 mrc p15, 0, r0, c1, c0, 1 161 bx lr 162 163 RVCT_ASM_EXPORT ArmWriteCpuActlr 164 mcr p15, 0, r0, c1, c0, 1 165 dsb 166 isb 167 bx lr 168 169 END 170