1 /** @file
2 *
3 * Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
4 *
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
9 *
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 *
13 **/
14
15 #include <Uefi.h>
16 #include <Chipset/ArmV7.h>
17 #include <Library/BaseMemoryLib.h>
18 #include <Library/ArmLib.h>
19 #include <Library/BaseLib.h>
20 #include <Library/DebugLib.h>
21 #include "ArmV7Lib.h"
22 #include "ArmLibPrivate.h"
23 #include <Library/ArmArchTimer.h>
24
25 VOID
26 EFIAPI
ArmArchTimerReadReg(IN ARM_ARCH_TIMER_REGS Reg,OUT VOID * DstBuf)27 ArmArchTimerReadReg (
28 IN ARM_ARCH_TIMER_REGS Reg,
29 OUT VOID *DstBuf
30 )
31 {
32 // Check if the Generic/Architecture timer is implemented
33 if (ArmIsArchTimerImplemented ()) {
34 switch (Reg) {
35 case CntFrq:
36 *((UINTN *)DstBuf) = ArmReadCntFrq ();
37 return;
38
39 case CntPct:
40 *((UINT64 *)DstBuf) = ArmReadCntPct ();
41 return;
42
43 case CntkCtl:
44 *((UINTN *)DstBuf) = ArmReadCntkCtl();
45 return;
46
47 case CntpTval:
48 *((UINTN *)DstBuf) = ArmReadCntpTval ();
49 return;
50
51 case CntpCtl:
52 *((UINTN *)DstBuf) = ArmReadCntpCtl ();
53 return;
54
55 case CntvTval:
56 *((UINTN *)DstBuf) = ArmReadCntvTval ();
57 return;
58
59 case CntvCtl:
60 *((UINTN *)DstBuf) = ArmReadCntvCtl ();
61 return;
62
63 case CntvCt:
64 *((UINT64 *)DstBuf) = ArmReadCntvCt ();
65 return;
66
67 case CntpCval:
68 *((UINT64 *)DstBuf) = ArmReadCntpCval ();
69 return;
70
71 case CntvCval:
72 *((UINT64 *)DstBuf) = ArmReadCntvCval ();
73 return;
74
75 case CntvOff:
76 *((UINT64 *)DstBuf) = ArmReadCntvOff ();
77 return;
78
79 case CnthCtl:
80 case CnthpTval:
81 case CnthpCtl:
82 case CnthpCval:
83 DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
84 break;
85
86 default:
87 DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
88 }
89 } else {
90 DEBUG ((EFI_D_ERROR, "Attempt to read ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
91 ASSERT (0);
92 }
93
94 *((UINT64 *)DstBuf) = 0;
95 }
96
97 VOID
98 EFIAPI
ArmArchTimerWriteReg(IN ARM_ARCH_TIMER_REGS Reg,IN VOID * SrcBuf)99 ArmArchTimerWriteReg (
100 IN ARM_ARCH_TIMER_REGS Reg,
101 IN VOID *SrcBuf
102 )
103 {
104 // Check if the Generic/Architecture timer is implemented
105 if (ArmIsArchTimerImplemented ()) {
106
107 switch (Reg) {
108
109 case CntFrq:
110 ArmWriteCntFrq (*((UINTN *)SrcBuf));
111 break;
112
113 case CntPct:
114 DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTPCT \n"));
115 break;
116
117 case CntkCtl:
118 ArmWriteCntkCtl (*((UINTN *)SrcBuf));
119 break;
120
121 case CntpTval:
122 ArmWriteCntpTval (*((UINTN *)SrcBuf));
123 break;
124
125 case CntpCtl:
126 ArmWriteCntpCtl (*((UINTN *)SrcBuf));
127 break;
128
129 case CntvTval:
130 ArmWriteCntvTval (*((UINTN *)SrcBuf));
131 break;
132
133 case CntvCtl:
134 ArmWriteCntvCtl (*((UINTN *)SrcBuf));
135 break;
136
137 case CntvCt:
138 DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTVCT \n"));
139 break;
140
141 case CntpCval:
142 ArmWriteCntpCval (*((UINT64 *)SrcBuf) );
143 break;
144
145 case CntvCval:
146 ArmWriteCntvCval (*((UINT64 *)SrcBuf) );
147 break;
148
149 case CntvOff:
150 ArmWriteCntvOff (*((UINT64 *)SrcBuf));
151 break;
152
153 case CnthCtl:
154 case CnthpTval:
155 case CnthpCtl:
156 case CnthpCval:
157 DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
158 break;
159
160 default:
161 DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
162 }
163 } else {
164 DEBUG ((EFI_D_ERROR, "Attempt to write to ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
165 ASSERT (0);
166 }
167 }
168