1 /** @file 2 * 3 * Copyright (c) 2011-2016, ARM Limited. All rights reserved. 4 * 5 * This program and the accompanying materials 6 * are licensed and made available under the terms and conditions of the BSD License 7 * which accompanies this distribution. The full text of the license may be found at 8 * http://opensource.org/licenses/bsd-license.php 9 * 10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 * 13 **/ 14 15 #include <Library/ArmPlatformLib.h> 16 #include <Library/DebugLib.h> 17 #include <Library/HobLib.h> 18 #include <Library/PcdLib.h> 19 #include <Library/IoLib.h> 20 #include <Library/MemoryAllocationLib.h> 21 #include <ArmPlatform.h> 22 23 // Number of Virtual Memory Map Descriptors 24 #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 8 25 26 // DDR attributes 27 #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK 28 #define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED 29 30 /** 31 Return the Virtual Memory Map of your platform 32 33 This Virtual Memory Map is used by MemoryInitPei Module to initialize 34 the MMU on your platform. 35 36 @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR 37 describing a Physical-to-Virtual Memory 38 mapping. This array must be ended by a 39 zero-filled entry. 40 41 **/ 42 VOID ArmPlatformGetVirtualMemoryMap(IN ARM_MEMORY_REGION_DESCRIPTOR ** VirtualMemoryMap)43ArmPlatformGetVirtualMemoryMap ( 44 IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap 45 ) 46 { 47 ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; 48 EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; 49 UINTN Index = 0; 50 ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; 51 UINT32 SysId; 52 BOOLEAN HasSparseMemory; 53 EFI_VIRTUAL_ADDRESS SparseMemoryBase; 54 UINT64 SparseMemorySize; 55 56 ASSERT (VirtualMemoryMap != NULL); 57 58 // The FVP model has Sparse memory 59 SysId = MmioRead32 (ARM_VE_SYS_ID_REG); 60 if (SysId != ARM_RTSM_SYS_ID) { 61 HasSparseMemory = TRUE; 62 63 ResourceAttributes = 64 EFI_RESOURCE_ATTRIBUTE_PRESENT | 65 EFI_RESOURCE_ATTRIBUTE_INITIALIZED | 66 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | 67 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | 68 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | 69 EFI_RESOURCE_ATTRIBUTE_TESTED; 70 71 // Declared the additional DRAM from 2GB to 4GB 72 SparseMemoryBase = 0x0880000000; 73 SparseMemorySize = SIZE_2GB; 74 75 BuildResourceDescriptorHob ( 76 EFI_RESOURCE_SYSTEM_MEMORY, 77 ResourceAttributes, 78 SparseMemoryBase, 79 SparseMemorySize); 80 } else { 81 HasSparseMemory = FALSE; 82 SparseMemoryBase = 0x0; 83 SparseMemorySize = 0x0; 84 } 85 86 VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*) 87 AllocatePages (EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) 88 * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); 89 if (VirtualMemoryTable == NULL) { 90 return; 91 } 92 93 CacheAttributes = (FeaturePcdGet(PcdCacheEnable)) 94 ? DDR_ATTRIBUTES_CACHED 95 : DDR_ATTRIBUTES_UNCACHED; 96 97 // ReMap (Either NOR Flash or DRAM) 98 VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE; 99 VirtualMemoryTable[Index].VirtualBase = ARM_VE_REMAP_BASE; 100 VirtualMemoryTable[Index].Length = ARM_VE_REMAP_SZ; 101 VirtualMemoryTable[Index].Attributes = CacheAttributes; 102 103 // DDR 104 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE; 105 VirtualMemoryTable[Index].VirtualBase = ARM_VE_DRAM_BASE; 106 VirtualMemoryTable[Index].Length = ARM_VE_DRAM_SZ; 107 VirtualMemoryTable[Index].Attributes = CacheAttributes; 108 109 // CPU peripherals. TRM. Manual says not all of them are implemented. 110 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ON_CHIP_PERIPH_BASE; 111 VirtualMemoryTable[Index].VirtualBase = ARM_VE_ON_CHIP_PERIPH_BASE; 112 VirtualMemoryTable[Index].Length = ARM_VE_ON_CHIP_PERIPH_SZ; 113 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; 114 115 // SMB CS0-CS1 - NOR Flash 1 & 2 116 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE; 117 VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE; 118 VirtualMemoryTable[Index].Length = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ; 119 VirtualMemoryTable[Index].Attributes = CacheAttributes; 120 121 // SMB CS2 - SRAM 122 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE; 123 VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE; 124 VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ; 125 VirtualMemoryTable[Index].Attributes = CacheAttributes; 126 127 // Peripheral CS2 and CS3 128 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE; 129 VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE; 130 VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ; 131 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; 132 133 // Map sparse memory region if present 134 if (HasSparseMemory) { 135 VirtualMemoryTable[++Index].PhysicalBase = SparseMemoryBase; 136 VirtualMemoryTable[Index].VirtualBase = SparseMemoryBase; 137 VirtualMemoryTable[Index].Length = SparseMemorySize; 138 VirtualMemoryTable[Index].Attributes = CacheAttributes; 139 } 140 141 // End of Table 142 VirtualMemoryTable[++Index].PhysicalBase = 0; 143 VirtualMemoryTable[Index].VirtualBase = 0; 144 VirtualMemoryTable[Index].Length = 0; 145 VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; 146 147 ASSERT (Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); 148 *VirtualMemoryMap = VirtualMemoryTable; 149 } 150