1// 2// Copyright (c) 2011-2012, ARM Limited. All rights reserved. 3// 4// This program and the accompanying materials 5// are licensed and made available under the terms and conditions of the BSD License 6// which accompanies this distribution. The full text of the license may be found at 7// http://opensource.org/licenses/bsd-license.php 8// 9// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 10// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 11// 12// 13 14#include <Base.h> 15#include <Library/ArmPlatformLib.h> 16#include <Drivers/PL35xSmc.h> 17#include <ArmPlatform.h> 18#include <AutoGen.h> 19 20 INCLUDE AsmMacroIoLib.inc 21 22 EXPORT ArmPlatformSecBootAction 23 EXPORT ArmPlatformSecBootMemoryInit 24 IMPORT PL35xSmcInitialize 25 26 PRESERVE8 27 AREA CTA9x4BootMode, CODE, READONLY 28 29// 30// For each Chip Select: ChipSelect / SetCycle / SetOpMode 31// 32VersatileExpressSmcConfiguration 33 // NOR Flash 0 34 DCD PL350_SMC_DIRECT_CMD_ADDR_CS(0) 35 DCD PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1) 36 DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV 37 38 // NOR Flash 1 39 DCD PL350_SMC_DIRECT_CMD_ADDR_CS(4) 40 DCD PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1) 41 DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV 42 43 // SRAM 44 DCD PL350_SMC_DIRECT_CMD_ADDR_CS(2) 45 DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0x8) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1) 46 DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_ADV 47 48 // Usb/Eth/VRAM 49 DCD PL350_SMC_DIRECT_CMD_ADDR_CS(3) 50 DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x3) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x6) 51 DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC 52 53 // Memory Mapped Peripherals 54 DCD PL350_SMC_DIRECT_CMD_ADDR_CS(7) 55 DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1) 56 DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC 57 58 // VRAM 59 DCD PL350_SMC_DIRECT_CMD_ADDR_CS(1) 60 DCD 0x00049249 61 DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC 62VersatileExpressSmcConfigurationEnd 63 64/** 65 Call at the beginning of the platform boot up 66 67 This function allows the firmware platform to do extra actions at the early 68 stage of the platform power up. 69 70 Note: This function must be implemented in assembler as there is no stack set up yet 71 72**/ 73ArmPlatformSecBootAction 74 bx lr 75 76/** 77 Initialize the memory where the initial stacks will reside 78 79 This memory can contain the initial stacks (Secure and Secure Monitor stacks). 80 In some platform, this region is already initialized and the implementation of this function can 81 do nothing. This memory can also represent the Secure RAM. 82 This function is called before the satck has been set up. Its implementation must ensure the stack 83 pointer is not used (probably required to use assembly language) 84 85**/ 86ArmPlatformSecBootMemoryInit 87 mov r5, lr 88 89 // 90 // Initialize PL354 SMC 91 // 92 mov32 r1, ARM_VE_SMC_CTRL_BASE 93 ldr r2, =VersatileExpressSmcConfiguration 94 ldr r3, =VersatileExpressSmcConfigurationEnd 95 blx PL35xSmcInitialize 96 97 // 98 // Page mode setup for VRAM 99 // 100 mov32 r2, VRAM_MOTHERBOARD_BASE 101 102 // Read current state 103 ldr r0, [r2, #0] 104 ldr r0, [r2, #0] 105 ldr r0, = 0x00000000 106 str r0, [r2, #0] 107 ldr r0, [r2, #0] 108 109 // Enable page mode 110 ldr r0, [r2, #0] 111 ldr r0, [r2, #0] 112 ldr r0, = 0x00000000 113 str r0, [r2, #0] 114 ldr r0, = 0x00900090 115 str r0, [r2, #0] 116 117 // Confirm page mode enabled 118 ldr r0, [r2, #0] 119 ldr r0, [r2, #0] 120 ldr r0, = 0x00000000 121 str r0, [r2, #0] 122 ldr r0, [r2, #0] 123 124 bx r5 125 126 END 127