1// 2// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. 3// 4// This program and the accompanying materials 5// are licensed and made available under the terms and conditions of the BSD License 6// which accompanies this distribution. The full text of the license may be found at 7// http://opensource.org/licenses/bsd-license.php 8// 9// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 10// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 11// 12// 13 14#include <AsmMacroIoLibV8.h> 15#include <Base.h> 16#include <Library/ArmPlatformLib.h> 17#include <AutoGen.h> 18#include <ArmPlatform.h> 19 20.text 21.align 3 22 23GCC_ASM_EXPORT(ArmPlatformSecBootAction) 24GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit) 25GCC_ASM_EXPORT(ArmSecMpCoreSecondariesWrite) 26GCC_ASM_EXPORT(ArmSecMpCoreSecondariesRead) 27 28/** 29 Call at the beginning of the platform boot up 30 31 This function allows the firmware platform to do extra actions at the early 32 stage of the platform power up. 33 34 Note: This function must be implemented in assembler as there is no stack set up yet 35 36**/ 37ASM_PFX(ArmPlatformSecBootAction): 38 ret 39 40/** 41 Initialize the memory where the initial stacks will reside 42 43 This memory can contain the initial stacks (Secure and Secure Monitor stacks). 44 In some platform, this region is already initialized and the implementation of this function can 45 do nothing. This memory can also represent the Secure RAM. 46 This function is called before the satck has been set up. Its implementation must ensure the stack 47 pointer is not used (probably required to use assembly language) 48 49**/ 50ASM_PFX(ArmPlatformSecBootMemoryInit): 51 // The SMC does not need to be initialized for RTSM 52 ret 53 54/* Write the flag register used to start Secondary cores */ 55ASM_PFX(ArmSecMpCoreSecondariesWrite): 56 // Write to the CPU Mailbox 57 ret 58 59/* Read the flag register used to start Secondary cores */ 60ASM_PFX(ArmSecMpCoreSecondariesRead): 61 // Return the value from the CPU Mailbox 62 mov x0, #0 63 ret 64 65