1 /** @file 2 3 The definition for UHCI register operation routines. 4 5 Copyright (c) 2007, Intel Corporation. All rights reserved.<BR> 6 This program and the accompanying materials 7 are licensed and made available under the terms and conditions of the BSD License 8 which accompanies this distribution. The full text of the license may be found at 9 http://opensource.org/licenses/bsd-license.php 10 11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 14 **/ 15 16 #ifndef _EFI_UHCI_QUEUE_H_ 17 #define _EFI_UHCI_QUEUE_H_ 18 19 // 20 // Macroes used to set various links in UHCI's driver. 21 // In this UHCI driver, QH's horizontal link always pointers to other QH, 22 // and its vertical link always pointers to TD. TD's next pointer always 23 // pointers to other sibling TD. Frame link always pointers to QH because 24 // ISO transfer isn't supported. 25 // 26 // We should use UINT32 to access these pointers to void race conditions 27 // with hardware. 28 // 29 #define QH_HLINK(Pointer, Terminate) \ 30 (((UINT32) ((UINTN) (Pointer)) & 0xFFFFFFF0) | 0x02 | ((Terminate) ? 0x01 : 0)) 31 32 #define QH_VLINK(Pointer, Terminate) \ 33 (((UINT32) ((UINTN) (Pointer)) & 0xFFFFFFF0) | ((Terminate) ? 0x01 : 0)) 34 35 #define TD_LINK(Pointer, VertFirst, Terminate) \ 36 (((UINT32) ((UINTN) (Pointer)) & 0xFFFFFFF0) | \ 37 ((VertFirst) ? 0x04 : 0) | ((Terminate) ? 0x01 : 0)) 38 39 #define LINK_TERMINATED(Link) (((Link) & 0x01) != 0) 40 41 #define UHCI_ADDR(QhOrTd) ((VOID *) (UINTN) ((QhOrTd) & 0xFFFFFFF0)) 42 43 #pragma pack(1) 44 // 45 // Both links in QH has this internal structure: 46 // Next pointer: 28, Reserved: 2, NextIsQh: 1, Terminate: 1 47 // This is the same as frame list entry. 48 // 49 typedef struct { 50 UINT32 HorizonLink; 51 UINT32 VerticalLink; 52 } UHCI_QH_HW; 53 54 // 55 // Next link in TD has this internal structure: 56 // Next pointer: 28, Reserved: 1, Vertical First: 1, NextIsQh: 1, Terminate: 1 57 // 58 typedef struct { 59 UINT32 NextLink; 60 UINT32 ActualLen : 11; 61 UINT32 Reserved1 : 5; 62 UINT32 Status : 8; 63 UINT32 IntOnCpl : 1; 64 UINT32 IsIsoch : 1; 65 UINT32 LowSpeed : 1; 66 UINT32 ErrorCount : 2; 67 UINT32 ShortPacket : 1; 68 UINT32 Reserved2 : 2; 69 UINT32 PidCode : 8; 70 UINT32 DeviceAddr : 7; 71 UINT32 EndPoint : 4; 72 UINT32 DataToggle : 1; 73 UINT32 Reserved3 : 1; 74 UINT32 MaxPacketLen: 11; 75 UINT32 DataBuffer; 76 } UHCI_TD_HW; 77 #pragma pack() 78 79 typedef struct _UHCI_TD_SW UHCI_TD_SW; 80 typedef struct _UHCI_QH_SW UHCI_QH_SW; 81 82 struct _UHCI_QH_SW { 83 UHCI_QH_HW QhHw; 84 UHCI_QH_SW *NextQh; 85 UHCI_TD_SW *TDs; 86 UINTN Interval; 87 }; 88 89 struct _UHCI_TD_SW { 90 UHCI_TD_HW TdHw; 91 UHCI_TD_SW *NextTd; 92 UINT8 *Data; 93 UINT16 DataLen; 94 }; 95 96 97 /** 98 Link the TD To QH. 99 100 @param Uhc The UHCI device. 101 @param Qh The queue head for the TD to link to. 102 @param Td The TD to link. 103 104 **/ 105 VOID 106 UhciLinkTdToQh ( 107 IN USB_HC_DEV *Uhc, 108 IN UHCI_QH_SW *Qh, 109 IN UHCI_TD_SW *Td 110 ); 111 112 113 /** 114 Unlink TD from the QH. 115 116 @param Qh The queue head to unlink from. 117 @param Td The TD to unlink. 118 119 @return None. 120 121 **/ 122 VOID 123 UhciUnlinkTdFromQh ( 124 IN UHCI_QH_SW *Qh, 125 IN UHCI_TD_SW *Td 126 ); 127 128 129 /** 130 Map address of request structure buffer. 131 132 @param Uhc The UHCI device. 133 @param Request The user request buffer. 134 @param MappedAddr Mapped address of request. 135 @param Map Identificaion of this mapping to return. 136 137 @return EFI_SUCCESS Success. 138 @return EFI_DEVICE_ERROR Fail to map the user request. 139 140 **/ 141 EFI_STATUS 142 UhciMapUserRequest ( 143 IN USB_HC_DEV *Uhc, 144 IN OUT VOID *Request, 145 OUT UINT8 **MappedAddr, 146 OUT VOID **Map 147 ); 148 149 150 /** 151 Map address of user data buffer. 152 153 @param Uhc The UHCI device. 154 @param Direction Direction of the data transfer. 155 @param Data The user data buffer. 156 @param Len Length of the user data. 157 @param PktId Packet identificaion. 158 @param MappedAddr Mapped address to return. 159 @param Map Identificaion of this mapping to return. 160 161 @return EFI_SUCCESS Success. 162 @return EFI_DEVICE_ERROR Fail to map the user data. 163 164 **/ 165 EFI_STATUS 166 UhciMapUserData ( 167 IN USB_HC_DEV *Uhc, 168 IN EFI_USB_DATA_DIRECTION Direction, 169 IN VOID *Data, 170 IN OUT UINTN *Len, 171 OUT UINT8 *PktId, 172 OUT UINT8 **MappedAddr, 173 OUT VOID **Map 174 ); 175 176 177 /** 178 Delete a list of TDs. 179 180 @param Uhc The UHCI device. 181 @param FirstTd TD link list head. 182 183 @return None. 184 185 **/ 186 VOID 187 UhciDestoryTds ( 188 IN USB_HC_DEV *Uhc, 189 IN UHCI_TD_SW *FirstTd 190 ); 191 192 193 /** 194 Create an initialize a new queue head. 195 196 @param Uhc The UHCI device. 197 @param Interval The polling interval for the queue. 198 199 @return The newly created queue header. 200 201 **/ 202 UHCI_QH_SW * 203 UhciCreateQh ( 204 IN USB_HC_DEV *Uhc, 205 IN UINTN Interval 206 ); 207 208 209 /** 210 Create Tds list for Control Transfer. 211 212 @param Uhc The UHCI device. 213 @param DeviceAddr The device address. 214 @param DataPktId Packet Identification of Data Tds. 215 @param Request A pointer to cpu memory address of request structure buffer to transfer. 216 @param RequestPhy A pointer to pci memory address of request structure buffer to transfer. 217 @param Data A pointer to cpu memory address of user data buffer to transfer. 218 @param DataPhy A pointer to pci memory address of user data buffer to transfer. 219 @param DataLen Length of user data to transfer. 220 @param MaxPacket Maximum packet size for control transfer. 221 @param IsLow Full speed or low speed. 222 223 @return The Td list head for the control transfer. 224 225 **/ 226 UHCI_TD_SW * 227 UhciCreateCtrlTds ( 228 IN USB_HC_DEV *Uhc, 229 IN UINT8 DeviceAddr, 230 IN UINT8 DataPktId, 231 IN UINT8 *Request, 232 IN UINT8 *RequestPhy, 233 IN UINT8 *Data, 234 IN UINT8 *DataPhy, 235 IN UINTN DataLen, 236 IN UINT8 MaxPacket, 237 IN BOOLEAN IsLow 238 ); 239 240 241 /** 242 Create Tds list for Bulk/Interrupt Transfer. 243 244 @param Uhc USB_HC_DEV. 245 @param DevAddr Address of Device. 246 @param EndPoint Endpoint Number. 247 @param PktId Packet Identification of Data Tds. 248 @param Data A pointer to cpu memory address of user data buffer to transfer. 249 @param DataPhy A pointer to pci memory address of user data buffer to transfer. 250 @param DataLen Length of user data to transfer. 251 @param DataToggle Data Toggle Pointer. 252 @param MaxPacket Maximum packet size for Bulk/Interrupt transfer. 253 @param IsLow Is Low Speed Device. 254 255 @return The Tds list head for the bulk transfer. 256 257 **/ 258 UHCI_TD_SW * 259 UhciCreateBulkOrIntTds ( 260 IN USB_HC_DEV *Uhc, 261 IN UINT8 DevAddr, 262 IN UINT8 EndPoint, 263 IN UINT8 PktId, 264 IN UINT8 *Data, 265 IN UINT8 *DataPhy, 266 IN UINTN DataLen, 267 IN OUT UINT8 *DataToggle, 268 IN UINT8 MaxPacket, 269 IN BOOLEAN IsLow 270 ); 271 272 #endif 273