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1 /** @file
2   Set a IDT entry for debug purpose
3 
4   Set a IDT entry for interrupt vector 3 for debug purpose for x64 platform
5 
6 Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
7 
8 This program and the accompanying materials
9 are licensed and made available under the terms and conditions of the BSD License
10 which accompanies this distribution.  The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
12 
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 
16 **/
17 #include "ScriptExecute.h"
18 
19 //
20 // 8 extra pages for PF handler.
21 //
22 #define EXTRA_PAGE_TABLE_PAGES      8
23 
24 #define IA32_PG_P                   BIT0
25 #define IA32_PG_RW                  BIT1
26 #define IA32_PG_PS                  BIT7
27 
28 UINT64                              mPhyMask;
29 VOID                                *mOriginalHandler;
30 UINTN                               mPageFaultBuffer;
31 UINTN                               mPageFaultIndex = 0;
32 //
33 // Store the uplink information for each page being used.
34 //
35 UINT64                              *mPageFaultUplink[EXTRA_PAGE_TABLE_PAGES];
36 
37 /**
38   Page fault handler.
39 
40 **/
41 VOID
42 EFIAPI
43 PageFaultHandlerHook (
44   VOID
45   );
46 
47 /**
48   Hook IDT with our page fault handler so that the on-demand paging works on page fault.
49 
50   @param  IdtEntry  a pointer to IDT entry
51 
52 **/
53 VOID
HookPageFaultHandler(IN IA32_IDT_GATE_DESCRIPTOR * IdtEntry)54 HookPageFaultHandler (
55   IN IA32_IDT_GATE_DESCRIPTOR                   *IdtEntry
56   )
57 {
58   UINT32         RegEax;
59   UINT8          PhysicalAddressBits;
60   UINTN          PageFaultHandlerHookAddress;
61 
62   AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
63   if (RegEax >= 0x80000008) {
64     AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
65     PhysicalAddressBits = (UINT8) RegEax;
66   } else {
67     PhysicalAddressBits = 36;
68   }
69   mPhyMask = LShiftU64 (1, PhysicalAddressBits) - 1;
70   mPhyMask &= (1ull << 48) - SIZE_4KB;
71 
72   //
73   // Set Page Fault entry to catch >4G access
74   //
75   PageFaultHandlerHookAddress = (UINTN)PageFaultHandlerHook;
76   mOriginalHandler = (VOID *)(UINTN)(LShiftU64 (IdtEntry->Bits.OffsetUpper, 32) + IdtEntry->Bits.OffsetLow + (IdtEntry->Bits.OffsetHigh << 16));
77   IdtEntry->Bits.OffsetLow      = (UINT16)PageFaultHandlerHookAddress;
78   IdtEntry->Bits.Selector       = (UINT16)AsmReadCs ();
79   IdtEntry->Bits.Reserved_0     = 0;
80   IdtEntry->Bits.GateType       = IA32_IDT_GATE_TYPE_INTERRUPT_32;
81   IdtEntry->Bits.OffsetHigh     = (UINT16)(PageFaultHandlerHookAddress >> 16);
82   IdtEntry->Bits.OffsetUpper    = (UINT32)(PageFaultHandlerHookAddress >> 32);
83   IdtEntry->Bits.Reserved_1     = 0;
84 
85   if (mPage1GSupport) {
86     mPageFaultBuffer = (UINTN)(AsmReadCr3 () & mPhyMask) + EFI_PAGES_TO_SIZE(2);
87   }else {
88     mPageFaultBuffer = (UINTN)(AsmReadCr3 () & mPhyMask) + EFI_PAGES_TO_SIZE(6);
89   }
90   ZeroMem (mPageFaultUplink, sizeof (mPageFaultUplink));
91 }
92 
93 /**
94   The function will check if current waking vector is long mode.
95 
96   @param  AcpiS3Context                 a pointer to a structure of ACPI_S3_CONTEXT
97 
98   @retval TRUE   Current context need long mode waking vector.
99   @retval FALSE  Current context need not long mode waking vector.
100 **/
101 BOOLEAN
IsLongModeWakingVector(IN ACPI_S3_CONTEXT * AcpiS3Context)102 IsLongModeWakingVector (
103   IN ACPI_S3_CONTEXT                *AcpiS3Context
104   )
105 {
106   EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE  *Facs;
107 
108   Facs = (EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *) ((UINTN) (AcpiS3Context->AcpiFacsTable));
109   if ((Facs == NULL) ||
110       (Facs->Signature != EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) ||
111       ((Facs->FirmwareWakingVector == 0) && (Facs->XFirmwareWakingVector == 0)) ) {
112     // Something wrong with FACS
113     return FALSE;
114   }
115   if (Facs->XFirmwareWakingVector != 0) {
116     if ((Facs->Version == EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION) &&
117         ((Facs->Flags & EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F) != 0) &&
118         ((Facs->Flags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) {
119       // Both BIOS and OS wants 64bit vector
120       if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
121         return TRUE;
122       }
123     }
124   }
125   return FALSE;
126 }
127 
128 /**
129   Set a IDT entry for interrupt vector 3 for debug purpose.
130 
131   @param  AcpiS3Context  a pointer to a structure of ACPI_S3_CONTEXT
132 
133 **/
134 VOID
SetIdtEntry(IN ACPI_S3_CONTEXT * AcpiS3Context)135 SetIdtEntry (
136   IN ACPI_S3_CONTEXT     *AcpiS3Context
137   )
138 {
139   IA32_IDT_GATE_DESCRIPTOR                      *IdtEntry;
140   IA32_DESCRIPTOR                               *IdtDescriptor;
141   UINTN                                         S3DebugBuffer;
142   EFI_STATUS                                    Status;
143 
144   //
145   // Restore IDT for debug
146   //
147   IdtDescriptor = (IA32_DESCRIPTOR *) (UINTN) (AcpiS3Context->IdtrProfile);
148   AsmWriteIdtr (IdtDescriptor);
149 
150   //
151   // Setup the default CPU exception handlers
152   //
153   Status = InitializeCpuExceptionHandlers (NULL);
154   ASSERT_EFI_ERROR (Status);
155 
156   DEBUG_CODE (
157     //
158     // Update IDT entry INT3 if the instruction is valid in it
159     //
160     S3DebugBuffer = (UINTN) (AcpiS3Context->S3DebugBufferAddress);
161     if (*(UINTN *)S3DebugBuffer != (UINTN) -1) {
162       IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *)(IdtDescriptor->Base + (3 * sizeof (IA32_IDT_GATE_DESCRIPTOR)));
163       IdtEntry->Bits.OffsetLow      = (UINT16)S3DebugBuffer;
164       IdtEntry->Bits.Selector       = (UINT16)AsmReadCs ();
165       IdtEntry->Bits.Reserved_0     = 0;
166       IdtEntry->Bits.GateType       = IA32_IDT_GATE_TYPE_INTERRUPT_32;
167       IdtEntry->Bits.OffsetHigh     = (UINT16)(S3DebugBuffer >> 16);
168       IdtEntry->Bits.OffsetUpper    = (UINT32)(S3DebugBuffer >> 32);
169       IdtEntry->Bits.Reserved_1     = 0;
170     }
171   );
172 
173   //
174   // If both BIOS and OS wants long mode waking vector,
175   // S3ResumePei should have established 1:1 Virtual to Physical identity mapping page table,
176   // no need to hook page fault handler.
177   //
178   if (!IsLongModeWakingVector (AcpiS3Context)) {
179     IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *)(IdtDescriptor->Base + (14 * sizeof (IA32_IDT_GATE_DESCRIPTOR)));
180     HookPageFaultHandler (IdtEntry);
181   }
182 }
183 
184 /**
185   Acquire page for page fault.
186 
187   @param[in, out] Uplink        Pointer to up page table entry.
188 
189 **/
190 VOID
AcquirePage(IN OUT UINT64 * Uplink)191 AcquirePage (
192   IN OUT UINT64                 *Uplink
193   )
194 {
195   UINTN             Address;
196 
197   Address = mPageFaultBuffer + EFI_PAGES_TO_SIZE (mPageFaultIndex);
198   ZeroMem ((VOID *) Address, EFI_PAGES_TO_SIZE (1));
199 
200   //
201   // Cut the previous uplink if it exists and wasn't overwritten.
202   //
203   if ((mPageFaultUplink[mPageFaultIndex] != NULL) && ((*mPageFaultUplink[mPageFaultIndex] & mPhyMask) == Address)) {
204     *mPageFaultUplink[mPageFaultIndex] = 0;
205   }
206 
207   //
208   // Link & Record the current uplink.
209   //
210   *Uplink = Address | IA32_PG_P | IA32_PG_RW;
211   mPageFaultUplink[mPageFaultIndex] = Uplink;
212 
213   mPageFaultIndex = (mPageFaultIndex + 1) % EXTRA_PAGE_TABLE_PAGES;
214 }
215 
216 /**
217   The page fault handler that on-demand read >4G memory/MMIO.
218 
219   @retval TRUE     The page fault is correctly handled.
220   @retval FALSE    The page fault is not handled and is passed through to original handler.
221 
222 **/
223 BOOLEAN
224 EFIAPI
PageFaultHandler(VOID)225 PageFaultHandler (
226   VOID
227   )
228 {
229   UINT64         *PageTable;
230   UINT64         PFAddress;
231   UINTN          PTIndex;
232 
233   PFAddress = AsmReadCr2 ();
234   DEBUG ((EFI_D_ERROR, "BootScript - PageFaultHandler: Cr2 - %lx\n", PFAddress));
235 
236   if (PFAddress >= mPhyMask + SIZE_4KB) {
237     return FALSE;
238   }
239   PFAddress &= mPhyMask;
240 
241   PageTable = (UINT64*)(UINTN)(AsmReadCr3 () & mPhyMask);
242 
243   PTIndex = BitFieldRead64 (PFAddress, 39, 47);
244   // PML4E
245   if ((PageTable[PTIndex] & IA32_PG_P) == 0) {
246     AcquirePage (&PageTable[PTIndex]);
247   }
248   PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & mPhyMask);
249   PTIndex = BitFieldRead64 (PFAddress, 30, 38);
250   // PDPTE
251   if (mPage1GSupport) {
252     PageTable[PTIndex] = (PFAddress & ~((1ull << 30) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;
253   } else {
254     if ((PageTable[PTIndex] & IA32_PG_P) == 0) {
255       AcquirePage (&PageTable[PTIndex]);
256     }
257     PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & mPhyMask);
258     PTIndex = BitFieldRead64 (PFAddress, 21, 29);
259     // PD
260     PageTable[PTIndex] = (PFAddress & ~((1ull << 21) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;
261   }
262 
263   return TRUE;
264 }
265