1/** @file 2PCI express expansion ports 3 4Copyright (c) 2013-2015 Intel Corporation. 5 6This program and the accompanying materials 7are licensed and made available under the terms and conditions of the BSD License 8which accompanies this distribution. The full text of the license may be found at 9http://opensource.org/licenses/bsd-license.php 10 11THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 14**/ 15 16#ifndef PcieExpansionPrt_asi 17#define PcieExpansionPrt_asi 18 19Device (PEX0) // PCI express bus bridged from [Bus 0, Device 23, Function 0] 20{ 21 Name(_ADR,0x00170000) // Device (HI WORD)=23, Func (LO WORD)=0 22 Name(_PRW,Package(){0x11,0x03}) // GPE pin 0x11, Wake from S3 -- PCI PME# 23 24 OperationRegion (PES0,PCI_Config,0x40,0xA0) 25 Field (PES0, AnyAcc, NoLock, Preserve) 26 { 27 Offset(0x1A), // SLSTS - Slot Status Register 28 ABP0, 1, // Bit 0, Attention Button Pressed 29 , 2, 30 PDC0, 1, // Bit 3, Presence Detect Changed 31 , 2, 32 PDS0, 1, // Bit 6, Presence Detect State 33 , 1, 34 LSC0, 1, // Bit 8, Link Active State Changed 35 offset (0x20), 36 , 16, 37 PMS0, 1, // Bit 16, PME Status 38 offset (0x98), 39 , 30, 40 HPE0, 1, // Bit 30, Hot Plug SCI Enable 41 PCE0, 1, // Bit 31, Power Management SCI Enable. 42 , 30, 43 HPS0, 1, // Bit 30, Hot Plug SCI Status 44 PCS0, 1, // Bit 31, Power Management SCI Status. 45 } 46 47 Method(_PRT,0,NotSerialized) { 48 If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing 49 { 50 Return ( 51 Package() 52 { 53 // Port 0: INTA->PIRQE,INTB->PIRQF,INTC->PIRQG,INTD->PIRQH 54 Package() {0x0000ffff, 0, \_SB_.PCI0.LPC.LNKE, 0}, // PCI Slot 1 55 Package() {0x0000ffff, 1, \_SB_.PCI0.LPC.LNKF, 0}, 56 Package() {0x0000ffff, 2, \_SB_.PCI0.LPC.LNKG, 0}, 57 Package() {0x0000ffff, 3, \_SB_.PCI0.LPC.LNKH, 0}, 58 } 59 ) 60 } 61 else // IOAPIC Routing 62 { 63 Return ( 64 Package() 65 { 66 // Port 0: INTA->PIRQE,INTB->PIRQF,INTC->PIRQG,INTD->PIRQH 67 Package() {0x0000ffff, 0, 0, 20}, // PCI Slot 1 68 Package() {0x0000ffff, 1, 0, 21}, 69 Package() {0x0000ffff, 2, 0, 22}, 70 Package() {0x0000ffff, 3, 0, 23}, 71 } 72 ) 73 } 74 } 75} 76 77Device (PEX1) // PCI express bus bridged from [Bus 0, Device 23, Function 1] 78{ 79 Name(_ADR,0x00170001) // Device (HI WORD)=23, Func (LO WORD)=1 80 Name(_PRW,Package(){0x11,0x03}) // GPE pin 0x11, Wake from S3 -- PCI PME# 81 OperationRegion (PES1,PCI_Config,0x40,0xA0) 82 Field (PES1, AnyAcc, NoLock, Preserve) 83 { 84 Offset(0x1A), // SLSTS - Slot Status Register 85 ABP1, 1, // Bit 0, Attention Button Pressed 86 , 2, 87 PDC1, 1, // Bit 3, Presence Detect Changed 88 , 2, 89 PDS1, 1, // Bit 6, Presence Detect State 90 , 1, 91 LSC1, 1, // Bit 8, Link Active State Changed 92 offset (0x20), 93 , 16, 94 PMS1, 1, // Bit 16, PME Status 95 offset (0x98), 96 , 30, 97 HPE1, 1, // Bit 30, Hot Plug SCI Enable 98 PCE1, 1, // Bit 31, Power Management SCI Enable. 99 , 30, 100 HPS1, 1, // Bit 30, Hot Plug SCI Status 101 PCS1, 1, // Bit 31, Power Management SCI Status. 102 } 103 Method(_PRT,0,NotSerialized) { 104 If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing 105 { 106 Return ( 107 Package() 108 { 109 // Port 1: INTA->PIRQF,INTB->PIRQG,INTC->PIRQH,INTD->PIRQE 110 Package() {0x0000ffff, 0, \_SB_.PCI0.LPC.LNKF, 0}, 111 Package() {0x0000ffff, 1, \_SB_.PCI0.LPC.LNKG, 0}, 112 Package() {0x0000ffff, 2, \_SB_.PCI0.LPC.LNKH, 0}, 113 Package() {0x0000ffff, 3, \_SB_.PCI0.LPC.LNKE, 0}, 114 } 115 ) 116 } 117 else // IOAPIC Routing 118 { 119 Return ( 120 Package() 121 { 122 // Port 1: INTA->PIRQF,INTB->PIRQG,INTC->PIRQH,INTD->PIRQE 123 Package() {0x0000ffff, 0, 0, 21}, 124 Package() {0x0000ffff, 1, 0, 22}, 125 Package() {0x0000ffff, 2, 0, 23}, 126 Package() {0x0000ffff, 3, 0, 20}, 127 } 128 ) 129 } 130 } 131} 132 133#endif 134