1 /** @file 2 MSR Definitions for Pentium Processors. 3 4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures 5 are provided for MSRs that contain one or more bit fields. If the MSR value 6 returned is a single 32-bit or 64-bit value, then a data structure is not 7 provided for that MSR. 8 9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> 10 This program and the accompanying materials 11 are licensed and made available under the terms and conditions of the BSD License 12 which accompanies this distribution. The full text of the license may be found at 13 http://opensource.org/licenses/bsd-license.php 14 15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 17 18 @par Specification Reference: 19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, 20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.22. 21 22 **/ 23 24 #ifndef __PENTIUM_MSR_H__ 25 #define __PENTIUM_MSR_H__ 26 27 #include <Register/ArchitecturalMsr.h> 28 29 /** 30 See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.". 31 32 @param ECX MSR_PENTIUM_P5_MC_ADDR (0x00000000) 33 @param EAX Lower 32-bits of MSR value. 34 @param EDX Upper 32-bits of MSR value. 35 36 <b>Example usage</b> 37 @code 38 UINT64 Msr; 39 40 Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_ADDR); 41 AsmWriteMsr64 (MSR_PENTIUM_P5_MC_ADDR, Msr); 42 @endcode 43 @note MSR_PENTIUM_P5_MC_ADDR is defined as P5_MC_ADDR in SDM. 44 **/ 45 #define MSR_PENTIUM_P5_MC_ADDR 0x00000000 46 47 48 /** 49 See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.". 50 51 @param ECX MSR_PENTIUM_P5_MC_TYPE (0x00000001) 52 @param EAX Lower 32-bits of MSR value. 53 @param EDX Upper 32-bits of MSR value. 54 55 <b>Example usage</b> 56 @code 57 UINT64 Msr; 58 59 Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_TYPE); 60 AsmWriteMsr64 (MSR_PENTIUM_P5_MC_TYPE, Msr); 61 @endcode 62 @note MSR_PENTIUM_P5_MC_TYPE is defined as P5_MC_TYPE in SDM. 63 **/ 64 #define MSR_PENTIUM_P5_MC_TYPE 0x00000001 65 66 67 /** 68 See Section 17.15, "Time-Stamp Counter.". 69 70 @param ECX MSR_PENTIUM_TSC (0x00000010) 71 @param EAX Lower 32-bits of MSR value. 72 @param EDX Upper 32-bits of MSR value. 73 74 <b>Example usage</b> 75 @code 76 UINT64 Msr; 77 78 Msr = AsmReadMsr64 (MSR_PENTIUM_TSC); 79 AsmWriteMsr64 (MSR_PENTIUM_TSC, Msr); 80 @endcode 81 @note MSR_PENTIUM_TSC is defined as TSC in SDM. 82 **/ 83 #define MSR_PENTIUM_TSC 0x00000010 84 85 86 /** 87 See Section 18.24.1, "Control and Event Select Register (CESR).". 88 89 @param ECX MSR_PENTIUM_CESR (0x00000011) 90 @param EAX Lower 32-bits of MSR value. 91 @param EDX Upper 32-bits of MSR value. 92 93 <b>Example usage</b> 94 @code 95 UINT64 Msr; 96 97 Msr = AsmReadMsr64 (MSR_PENTIUM_CESR); 98 AsmWriteMsr64 (MSR_PENTIUM_CESR, Msr); 99 @endcode 100 @note MSR_PENTIUM_CESR is defined as CESR in SDM. 101 **/ 102 #define MSR_PENTIUM_CESR 0x00000011 103 104 105 /** 106 Section 18.24.3, "Events Counted.". 107 108 @param ECX MSR_PENTIUM_CTRn 109 @param EAX Lower 32-bits of MSR value. 110 @param EDX Upper 32-bits of MSR value. 111 112 <b>Example usage</b> 113 @code 114 UINT64 Msr; 115 116 Msr = AsmReadMsr64 (MSR_PENTIUM_CTR0); 117 AsmWriteMsr64 (MSR_PENTIUM_CTR0, Msr); 118 @endcode 119 @note MSR_PENTIUM_CTR0 is defined as CTR0 in SDM. 120 MSR_PENTIUM_CTR1 is defined as CTR1 in SDM. 121 @{ 122 **/ 123 #define MSR_PENTIUM_CTR0 0x00000012 124 #define MSR_PENTIUM_CTR1 0x00000013 125 /// @} 126 127 #endif 128