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1/** @file
2  SSDT for RhProxy Driver.
3
4Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
5This program and the accompanying materials
6are licensed and made available under the terms and conditions of the BSD License
7which accompanies this distribution.  The full text of the license may be found at
8http://opensource.org/licenses/bsd-license.php
9
10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13**/
14
15DefinitionBlock ("RHPX.aml", "SSDT", 1, "MSFT", "RHPROXY", 1)
16{
17    Scope (\_SB)
18    {
19        //
20        // Test peripheral device node for MinnowBoardMax
21        //
22        Device(RHPX)
23        {
24            Name(_HID, "MSFT8000")
25            Name(_CID, "MSFT8000")
26            Name(_UID, 1)
27
28            Name(_CRS, ResourceTemplate()
29            {
30                // Index 0
31                SPISerialBus(            // Pin 5, 7, 9 , 11 of JP1 for SIO_SPI
32                    1,                     // Device selection
33                    PolarityLow,           // Device selection polarity
34                    FourWireMode,          // wiremode
35                    8,                     // databit len
36                    ControllerInitiated,   // slave mode
37                    8000000,               // Connection speed
38                    ClockPolarityLow,      // Clock polarity
39                    ClockPhaseSecond,      // clock phase
40                    "\\_SB.SPI1",          // ResourceSource: SPI bus controller name
41                    0,                     // ResourceSourceIndex
42                    ResourceConsumer,      // Resource usage
43                    JSPI,                  // DescriptorName: creates name for offset of resource descriptor
44                    )                      // Vendor Data
45
46                // Index 1
47                I2CSerialBus(            // Pin 13, 15 of JP1, for SIO_I2C5 (signal)
48                    0xFF,                  // SlaveAddress: bus address (TBD)
49                    ,                      // SlaveMode: default to ControllerInitiated
50                    400000,                // ConnectionSpeed: in Hz
51                    ,                      // Addressing Mode: default to 7 bit
52                    "\\_SB.I2C6",          // ResourceSource: I2C bus controller name (For MinnowBoard Max, hardware I2C5(0-based) is reported as ACPI I2C6(1-based))
53                    ,
54                    ,
55                    JI2C,                  // Descriptor Name: creates name for offset of resource descriptor
56                    )                      // VendorData
57
58                // Index 2
59                UARTSerialBus(           // Pin 17, 19 of JP1, for SIO_UART2
60                    115200,                // InitialBaudRate: in bits ber second
61                    ,                      // BitsPerByte: default to 8 bits
62                    ,                      // StopBits: Defaults to one bit
63                    0xfc,                  // LinesInUse: 8 1-bit flags to declare line enabled
64                    ,                      // IsBigEndian: default to LittleEndian
65                    ,                      // Parity: Defaults to no parity
66                    ,                      // FlowControl: Defaults to no flow control
67                    32,                    // ReceiveBufferSize
68                    32,                    // TransmitBufferSize
69                    "\\_SB.URT2",          // ResourceSource: UART bus controller name
70                    ,
71                    ,
72                    UAR2,                  // DescriptorName: creates name for offset of resource descriptor
73                    )
74
75                // Index 3
76                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {0}  // Pin 21 of JP1 (GPIO_S5[00])
77                // Index 4
78                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {0}
79
80                // Index 5
81                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {1}  // Pin 23 of JP1 (GPIO_S5[01])
82                // Index 6
83                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {1}
84
85                // Index 7
86                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {2}  // Pin 25 of JP1 (GPIO_S5[02])
87                // Index 8
88                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {2}
89
90                // Index 9
91                UARTSerialBus(           // Pin 6, 8, 10, 12 of JP1, for SIO_UART1
92                    115200,                // InitialBaudRate: in bits ber second
93                    ,                      // BitsPerByte: default to 8 bits
94                    ,                      // StopBits: Defaults to one bit
95                    0xfc,                  // LinesInUse: 8 1-bit flags to declare line enabled
96                    ,                      // IsBigEndian: default to LittleEndian
97                    ,                      // Parity: Defaults to no parity
98                    FlowControlHardware,   // FlowControl: Defaults to no flow control
99                    32,                    // ReceiveBufferSize
100                    32,                    // TransmitBufferSize
101                    "\\_SB.URT1",          // ResourceSource: UART bus controller name
102                    ,
103                    ,
104                    UAR1,              // DescriptorName: creates name for offset of resource descriptor
105                    )
106
107                // Index 10
108                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {62}  // Pin 14 of JP1 (GPIO_SC[62])
109                // Index 11
110                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {62}
111
112                // Index 12
113                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {63}  // Pin 16 of JP1 (GPIO_SC[63])
114                // Index 13
115                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {63}
116
117                // Index 14
118                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {65}  // Pin 18 of JP1 (GPIO_SC[65])
119                // Index 15
120                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {65}
121
122                // Index 16
123                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {64}  // Pin 20 of JP1 (GPIO_SC[64])
124                // Index 17
125                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {64}
126
127                // Index 18
128                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {94}  // Pin 22 of JP1 (GPIO_SC[94])
129                // Index 19
130                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {94}
131
132                // Index 20
133                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {95}  // Pin 24 of JP1 (GPIO_SC[95])
134                // Index 21
135                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {95}
136
137                // Index 22
138                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {54}  // Pin 26 of JP1 (GPIO_SC[54])
139                // Index 23
140                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {54}
141            })
142
143            Name(_DSD, Package()
144            {
145                ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
146                Package()
147                {
148                    // SPI Mapping
149                    Package(2) { "bus-SPI-SPI0", Package() { 0 }},
150
151                    // TODO: Intel will need to provide the right value for SPI0 properties
152                    Package(2) { "SPI0-MinClockInHz", 100000 },
153                    Package(2) { "SPI0-MaxClockInHz", 15000000 },
154                    // SupportedDataBitLengths takes a list of support data bit length
155                    // Example : Package(2) { "SPI0-SupportedDataBitLengths", Package() { 8, 7, 16 }},
156                    Package(2) { "SPI0-SupportedDataBitLengths", Package() { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 }},
157                    // I2C Mapping
158                    Package(2) { "bus-I2C-I2C5", Package() { 1 }},
159                    // UART Mapping
160                    Package(2) { "bus-UART-UART2", Package() { 2 }},
161                    Package(2) { "bus-UART-UART1", Package() { 9 }},
162                }
163            })
164        }
165    }
166}