1 2 /*++ 3 4 Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved 5 6 This program and the accompanying materials are licensed and made available under 7 the terms and conditions of the BSD License that accompanies this distribution. 8 The full text of the license may be found at 9 http://opensource.org/licenses/bsd-license.php. 10 11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 14 15 Module Name: 16 17 VlvPolicy.h 18 19 Abstract: 20 21 Interface definition details between ValleyView MRC and platform drivers during PEI phase. 22 23 --*/ 24 25 #ifndef _VLV_POLICY_PPI_H_ 26 #define _VLV_POLICY_PPI_H_ 27 28 // 29 // MRC Policy provided by platform for PEI phase {7D84B2C2-22A1-4372-B12C-EBB232D3A6A3} 30 // 31 #define VLV_POLICY_PPI_GUID \ 32 { \ 33 0x7D84B2C2, 0x22A1, 0x4372, 0xB1, 0x2C, 0xEB, 0xB2, 0x32, 0xD3, 0xA6, 0xA3 \ 34 } 35 36 // 37 // Extern the GUID for protocol users. 38 // 39 extern EFI_GUID gVlvPolicyPpiGuid; 40 41 // 42 // PPI revision number 43 // Any backwards compatible changes to this PPI will result in an update in the revision number 44 // Major changes will require publication of a new PPI 45 // 46 #define MRC_PLATFORM_POLICY_PPI_REVISION 1 47 48 #ifndef MAX_SOCKETS 49 #define MAX_SOCKETS 4 50 #endif 51 52 #define S3_TIMING_DATA_LEN 9 53 #define S3_READ_TRAINING_DATA_LEN 16 54 #define S3_WRITE_TRAINING_DATA_LEN 12 55 56 #ifndef S3_RESTORE_DATA_LEN 57 #define S3_RESTORE_DATA_LEN (S3_TIMING_DATA_LEN + S3_READ_TRAINING_DATA_LEN + S3_WRITE_TRAINING_DATA_LEN) 58 #endif // S3_RESTORE_DATA_LEN 59 #pragma pack(1) 60 // 61 // MRC Platform Data Structure 62 // 63 typedef struct { 64 UINT8 SpdAddressTable[MAX_SOCKETS]; 65 UINT8 TSonDimmSmbusAddress[MAX_SOCKETS]; 66 67 UINT16 SmbusBar; 68 UINT32 IchRcba; 69 UINT32 WdbBaseAddress; // Write Data Buffer area (WC caching mode) 70 UINT32 WdbRegionSize; 71 UINT32 SmBusAddress; 72 UINT8 UserBd; 73 UINT8 PlatformType; 74 UINT8 FastBoot; 75 UINT8 DynSR; 76 } VLV_PLATFORM_DATA; 77 78 79 typedef struct { 80 UINT16 MmioSize; 81 UINT16 GttSize; 82 UINT8 IgdDvmt50PreAlloc; 83 UINT8 PrimaryDisplay; 84 UINT8 PAVPMode; 85 UINT8 ApertureSize; 86 } GT_CONFIGURATION; 87 88 typedef struct { 89 UINT8 EccSupport; 90 UINT16 DdrFreqLimit; 91 UINT8 MaxTolud; 92 } MEMORY_CONFIGURATION; 93 94 95 // 96 // MRC Platform Policiy PPI 97 // 98 typedef struct _VLV_POLICY_PPI { 99 UINT8 Revision; 100 VLV_PLATFORM_DATA PlatformData; 101 GT_CONFIGURATION GtConfig; 102 MEMORY_CONFIGURATION MemConfig; 103 VOID *S3DataPtr; // was called MRC_PARAMS_SAVE_RESTORE 104 UINT8 ISPEn; //ISP (IUNIT) Device Enabled 105 UINT8 ISPPciDevConfig; //ISP (IUNIT) Device Config: 0->B0/D2/F0 for Window OS, 1->B0D3/F0 for Linux OS 106 } VLV_POLICY_PPI; 107 108 #pragma pack() 109 110 #endif // _VLV_POLICY_PPI_H_ 111