1 /*++ 2 3 Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved 4 5 This program and the accompanying materials are licensed and made available under 6 the terms and conditions of the BSD License that accompanies this distribution. 7 The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php. 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 13 14 15 Module Name: 16 17 I2CRegs.h 18 19 Abstract: 20 21 Register Definitions for I2C Driver/PEIM. 22 23 --*/ 24 #include <Uefi.h> 25 #include <Library/IoLib.h> 26 27 #ifndef I2C_REGS_A0_H 28 #define I2C_REGS_A0_H 29 30 // 31 // FIFO write workaround value. 32 // 33 #define FIFO_WRITE_DELAY 2 34 35 // 36 // MMIO Register Definitions 37 // 38 #define R_IC_CON ( 0x00) // I2C Control 39 #define B_IC_RESTART_EN BIT5 40 #define B_IC_SLAVE_DISABLE BIT6 41 #define V_SPEED_STANDARD 0x02 42 #define V_SPEED_FAST 0x04 43 #define V_SPEED_HIGH 0x06 44 #define B_MASTER_MODE BIT0 45 46 #define R_IC_TAR ( 0x04) // I2C Target Address 47 #define IC_TAR_10BITADDR_MASTER BIT12 48 49 #define R_IC_SAR ( 0x08) // I2C Slave Address 50 #define R_IC_HS_MADDR ( 0x0C) // I2C HS MasterMode Code Address 51 #define R_IC_DATA_CMD ( 0x10) // I2C Rx/Tx Data Buffer and Command 52 53 #define B_READ_CMD BIT8 // 1 = read, 0 = write 54 #define B_CMD_STOP BIT9 // 1 = STOP 55 #define B_CMD_RESTART BIT10 // 1 = IC_RESTART_EN 56 57 #define V_WRITE_CMD_MASK ( 0xFF) 58 59 #define R_IC_SS_SCL_HCNT ( 0x14) // Standard Speed I2C Clock SCL High Count 60 #define R_IC_SS_SCL_LCNT ( 0x18) // Standard Speed I2C Clock SCL Low Count 61 #define R_IC_FS_SCL_HCNT ( 0x1C) // Full Speed I2C Clock SCL High Count 62 #define R_IC_FS_SCL_LCNT ( 0x20) // Full Speed I2C Clock SCL Low Count 63 #define R_IC_HS_SCL_HCNT ( 0x24) // High Speed I2C Clock SCL High Count 64 #define R_IC_HS_SCL_LCNT ( 0x28) // High Speed I2C Clock SCL Low Count 65 #define R_IC_INTR_STAT ( 0x2C) // I2C Inetrrupt Status 66 #define R_IC_INTR_MASK ( 0x30) // I2C Interrupt Mask 67 #define I2C_INTR_GEN_CALL BIT11 // General call received 68 #define I2C_INTR_START_DET BIT10 69 #define I2C_INTR_STOP_DET BIT9 70 #define I2C_INTR_ACTIVITY BIT8 71 #define I2C_INTR_TX_ABRT BIT6 // Set on NACK 72 #define I2C_INTR_TX_EMPTY BIT4 73 #define I2C_INTR_TX_OVER BIT3 74 #define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold 75 #define I2C_INTR_RX_OVER BIT1 76 #define I2C_INTR_RX_UNDER BIT0 77 #define R_IC_RAW_INTR_STAT ( 0x34) // I2C Raw Interrupt Status 78 #define R_IC_RX_TL ( 0x38) // I2C Receive FIFO Threshold 79 #define R_IC_TX_TL ( 0x3C) // I2C Transmit FIFO Threshold 80 #define R_IC_CLR_INTR ( 0x40) // Clear Combined and Individual Interrupts 81 #define R_IC_CLR_RX_UNDER ( 0x44) // Clear RX_UNDER Interrupt 82 #define R_IC_CLR_RX_OVER ( 0x48) // Clear RX_OVERinterrupt 83 #define R_IC_CLR_TX_OVER ( 0x4C) // Clear TX_OVER interrupt 84 #define R_IC_CLR_RD_REQ ( 0x50) // Clear RD_REQ interrupt 85 #define R_IC_CLR_TX_ABRT ( 0x54) // Clear TX_ABRT interrupt 86 #define R_IC_CLR_RX_DONE ( 0x58) // Clear RX_DONE interrupt 87 #define R_IC_CLR_ACTIVITY ( 0x5C) // Clear ACTIVITY interrupt 88 #define R_IC_CLR_STOP_DET ( 0x60) // Clear STOP_DET interrupt 89 #define R_IC_CLR_START_DET ( 0x64) // Clear START_DET interrupt 90 #define R_IC_CLR_GEN_CALL ( 0x68) // Clear GEN_CALL interrupt 91 #define R_IC_ENABLE ( 0x6C) // I2C Enable 92 #define R_IC_STATUS ( 0x70) // I2C Status 93 94 #define R_IC_SDA_HOLD ( 0x7C) // I2C IC_DEFAULT_SDA_HOLD//16bits 95 96 #define STAT_MST_ACTIVITY BIT5 // Master FSM Activity Status. 97 #define STAT_RFF BIT4 // RX FIFO is completely full 98 #define STAT_RFNE BIT3 // RX FIFO is not empty 99 #define STAT_TFE BIT2 // TX FIFO is completely empty 100 #define STAT_TFNF BIT1 // TX FIFO is not full 101 102 #define R_IC_TXFLR ( 0x74) // Transmit FIFO Level Register 103 #define R_IC_RXFLR ( 0x78) // Receive FIFO Level Register 104 #define R_IC_TX_ABRT_SOURCE ( 0x80) // I2C Transmit Abort Status Register 105 #define R_IC_SLV_DATA_NACK_ONLY ( 0x84) // Generate SLV_DATA_NACK Register 106 #define R_IC_DMA_CR ( 0x88) // DMA Control Register 107 #define R_IC_DMA_TDLR ( 0x8C) // DMA Transmit Data Level 108 #define R_IC_DMA_RDLR ( 0x90) // DMA Receive Data Level 109 #define R_IC_SDA_SETUP ( 0x94) // I2C SDA Setup Register 110 #define R_IC_ACK_GENERAL_CALL ( 0x98) // I2C ACK General Call Register 111 #define R_IC_ENABLE_STATUS ( 0x9C) // I2C Enable Status Register 112 #define R_IC_COMP_PARAM ( 0xF4) // Component Parameter Register 113 #define R_IC_COMP_VERSION ( 0xF8) // Component Version ID 114 #define R_IC_COMP_TYPE ( 0xFC) // Component Type 115 116 #define R_IC_CLK_GATE ( 0xC0) // Clock Gate 117 118 #define I2C_SS_SCL_HCNT_VALUE_100M 0x1DD 119 #define I2C_SS_SCL_LCNT_VALUE_100M 0x1E4 120 #define I2C_FS_SCL_HCNT_VALUE_100M 0x54 121 #define I2C_FS_SCL_LCNT_VALUE_100M 0x9a 122 #define I2C_HS_SCL_HCNT_VALUE_100M 0x7 123 #define I2C_HS_SCL_LCNT_VALUE_100M 0xE 124 125 #define IC_TAR_10BITADDR_MASTER BIT12 126 #define FIFO_SIZE 32 127 #define R_IC_INTR_STAT ( 0x2C) // I2c Inetrrupt Status 128 #define R_IC_INTR_MASK ( 0x30) // I2c Interrupt Mask 129 #define I2C_INTR_GEN_CALL BIT11 // General call received 130 #define I2C_INTR_START_DET BIT10 131 #define I2C_INTR_STOP_DET BIT9 132 #define I2C_INTR_ACTIVITY BIT8 133 #define I2C_INTR_TX_ABRT BIT6 // Set on NACK 134 #define I2C_INTR_TX_EMPTY BIT4 135 #define I2C_INTR_TX_OVER BIT3 136 #define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold 137 #define I2C_INTR_RX_OVER BIT1 138 #define I2C_INTR_RX_UNDER BIT0 139 140 EFI_STATUS ProgramPciLpssI2C ( 141 IN UINT8 BusNo 142 ); 143 EFI_STATUS ByteReadI2C_Basic( 144 IN UINT8 BusNo, 145 IN UINT8 SlaveAddress, 146 IN UINTN ReadBytes, 147 OUT UINT8 *ReadBuffer, 148 IN UINT8 Start, 149 IN UINT8 End 150 ); 151 EFI_STATUS ByteWriteI2C_Basic( 152 IN UINT8 BusNo, 153 IN UINT8 SlaveAddress, 154 IN UINTN WriteBytes, 155 IN UINT8 *WriteBuffer, 156 IN UINT8 Start, 157 IN UINT8 End 158 ); 159 160 EFI_STATUS ByteReadI2C( 161 IN UINT8 BusNo, 162 IN UINT8 SlaveAddress, 163 IN UINT8 Offset, 164 IN UINTN ReadBytes, 165 OUT UINT8 *ReadBuffer 166 ); 167 EFI_STATUS ByteWriteI2C( 168 IN UINT8 BusNo, 169 IN UINT8 SlaveAddress, 170 IN UINT8 Offset, 171 IN UINTN WriteBytes, 172 IN UINT8 *WriteBuffer 173 ); 174 175 #endif // I2C_REGS_A0_H 176