1 /*******************************************************************************
2 * Copyright (C) 2018 Cadence Design Systems, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to use this Software with Cadence processor cores only and
7 * not with any other processors and platforms, subject to
8 * the following conditions:
9 *
10 * The above copyright notice and this permission notice shall be included
11 * in all copies or substantial portions of the Software.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
15 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
16 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
17 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
18 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
19 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20
21 ******************************************************************************/
22
23 /*******************************************************************************
24 * xf-main.c
25 *
26 * DSP processing framework main file
27 *
28 ******************************************************************************/
29
30 #define MODULE_TAG MAIN
31
32 /*******************************************************************************
33 * Includes
34 ******************************************************************************/
35
36 #include "xf.h"
37 #ifndef XAF_ENABLE_NON_HIKEY
38 volatile int waitstate;
39 #endif
40
41 #ifdef XAF_PROFILE_DSP
42 /* ... MCPS/profile info */
43 #include "xa_profiler.h"
44 #endif
45
46 /*******************************************************************************
47 * Global data definition
48 ******************************************************************************/
49 /* ...per-core execution data */
50 xf_core_data_t xf_core_data[XF_CFG_CORES_NUM];
51
52 /* ...AP-DSP shared memory pool */
53 xf_mm_pool_t xf_ap_shmem_pool;
54
55 /* ...per-core local memory pool */
56 xf_mm_pool_t xf_dsp_local_pool[XF_CFG_CORES_NUM];
57
58 #if XF_CFG_CORES_NUM > 1
59 /* ...DSP cluster shared memory pool */
60 xf_mm_pool_t xf_dsp_shmem_pool;
61 #endif
62
63 /* ...per-core shared memory with read-only access */
64 __xf_core_ro_data_t xf_core_ro_data[XF_CFG_CORES_NUM];
65
66 /* ...per-core shared memory with read-write access */
67 __xf_core_rw_data_t xf_core_rw_data[XF_CFG_CORES_NUM];
68
69 /*******************************************************************************
70 * Memory buffers - take them from linker file somehow - tbd
71 ******************************************************************************/
72
73 /* ...unallocated memory region - AP-DSP shared memory buffer - export from linker somehow */
74 //u8 xf_ap_shmem_buffer[XF_CFG_REMOTE_IPC_POOL_SIZE] __xf_shmem__;
75
76 #if XF_CFG_CORES_NUM > 1
77 /* ...unallocated DSP shared memory buffer */
78 u8 xf_dsp_shmem_buffer[XF_CFG_LOCAL_IPC_POOL_SIZE] __xf_shmem__;
79 #endif
80
81 /* ...unallocated per-core local memory (in 32-byte chunks) */
82 #ifdef XAF_ENABLE_NON_HIKEY
83 u8 xf_dsp_local_buffer[XF_CFG_CORES_NUM][XF_CFG_LOCAL_POOL_SIZE] __xf_mm__;
84 #else
85 u8 xf_dsp_local_buffer[XF_CFG_CORES_NUM][XF_CFG_LOCAL_POOL_SIZE];
86 //u8 g_tmp[2];
87 #endif
88
89 #ifdef XAF_PROFILE_DSP
90 xa_profiler prof;
91 #endif
92
93 /*******************************************************************************
94 * Timer interrupt - tbd
95 ******************************************************************************/
96
97 /*******************************************************************************
98 * IPC layer initialization
99 ******************************************************************************/
100
101 /* ...system-specific IPC layer initialization */
xf_ipc_init(u32 core)102 int xf_ipc_init(u32 core)
103 {
104 xf_core_data_t *cd = XF_CORE_DATA(core);
105 xf_shmem_data_t *shmem = (xf_shmem_data_t *)XF_CFG_SHMEM_ADDRESS(core);
106
107 /* ...initialize pointer to shared memory */
108 cd->shmem = (xf_shmem_handle_t *)shmem;
109 shmem->buffer = (uint8_t *) HIFI_MUSIC_DATA_LOCATION;
110 /* ...global memory pool initialization */
111 #ifdef XAF_ENABLE_NON_HIKEY
112 XF_CHK_API(xf_mm_init(&cd->shared_pool, shmem->buffer, XF_CFG_REMOTE_IPC_POOL_SIZE));
113 #else
114 XF_CHK_API(xf_mm_init(&cd->shared_pool, (void *) HIFI_MUSIC_DATA_LOCATION, XF_CFG_REMOTE_IPC_POOL_SIZE));
115 #endif
116 return 0;
117 }
118
119 /*******************************************************************************
120 * Core executive loop
121 ******************************************************************************/
122
xf_core_loop(u32 core)123 static void xf_core_loop(u32 core)
124 {
125 /* ...initialize internal core structures */
126 xf_core_init(core);
127
128 #ifdef XAF_PROFILE_DSP
129 /* Profiler initialization */
130 INIT_XA_PROFILER(prof,"DSP core");
131 #endif
132
133 for(;;)
134 {
135 /* ...wait in a low-power mode until event is triggered */
136 xf_ipi_wait(core);
137
138 /* ...service core event */
139 xf_core_service(core);
140 }
141 }
142
143 /*******************************************************************************
144 * Global entry point
145 ******************************************************************************/
146
main(void)147 int main(void)
148 {
149 #if XF_CFG_CORES_NUM > 1
150 u32 i;
151 #endif
152
153 /* ...reset ro/rw core data - tbd */
154 memset(xf_core_rw_data, 0, sizeof(xf_core_rw_data));
155 memset(xf_core_ro_data, 0, sizeof(xf_core_ro_data));
156
157 TRACE_INIT("Xtensa Audio DSP Codec Server");
158 #ifdef XAF_ENABLE_NON_HIKEY
159 /* ...initialize board */
160 xf_board_init();
161
162 /* ...global framework data initialization */
163 xf_global_init();
164 #endif
165
166 #if XF_CFG_CORES_NUM > 1
167 /* ...DSP shared memory pool initialization */
168 XF_CHK_API(xf_mm_init(&xf_dsp_shmem_pool, xf_dsp_shmem_buffer, XF_CFG_LOCAL_IPC_POOL_SIZE));
169 #endif
170
171 /* ...initialize per-core memory loop */
172 XF_CHK_API(xf_mm_init(&xf_core_data[0].local_pool, xf_dsp_local_buffer[0], XF_CFG_LOCAL_POOL_SIZE));
173
174 #if XF_CFG_CORES_NUM > 1
175 /* ...bring up all cores */
176 for (i = 1; i < XF_CFG_CORES_NUM; i++)
177 {
178 /* ...wake-up secondary core somehow and make it execute xf_core_loop */
179 xf_core_secondary_startup(i, xf_core_loop, i);
180
181 }
182 #endif
183
184 /* ...enter execution loop on master core #0 */
185 xf_core_loop(0);
186
187 /* ...not reachable */
188 return 0;
189 }
190