1 /*
2
3 Copyright (c) 2009, 2010, 2011, 2013 STMicroelectronics
4 Written by Christophe Lyon
5
6 Permission is hereby granted, free of charge, to any person obtaining a copy
7 of this software and associated documentation files (the "Software"), to deal
8 in the Software without restriction, including without limitation the rights
9 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 copies of the Software, and to permit persons to whom the Software is
11 furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 THE SOFTWARE.
23
24 */
25
26 #if defined(__arm__) || defined(__aarch64__)
27 #include <arm_neon.h>
28 #else
29 #include "stm-arm-neon.h"
30 #endif
31
32 #include "stm-arm-neon-ref.h"
33
exec_vldX_dup(void)34 void exec_vldX_dup (void)
35 {
36 /* In this case, input variables are arrays of vectors */
37 #define DECL_VLDX_DUP(T1, W, N, X) \
38 VECT_ARRAY_TYPE(T1, W, N, X) VECT_ARRAY_VAR(vector, T1, W, N, X); \
39 VECT_VAR_DECL(result_bis_##X, T1, W, N)[X * N]
40
41 /* We need to use a temporary result buffer (result_bis), because
42 the one used for other tests is not large enough. A subset of the
43 result data is moved from result_bis to result, and it is this
44 subset which is used to check the actual behaviour. The next
45 macro enables to move another chunk of data from result_bis to
46 result. */
47 #define TEST_VLDX_DUP(Q, T1, T2, W, N, X) \
48 VECT_ARRAY_VAR(vector, T1, W, N, X) = \
49 vld##X##Q##_dup_##T2##W(&VECT_VAR(buffer_dup, T1, W, N)[0]); \
50 \
51 vst##X##Q##_##T2##W(VECT_VAR(result_bis_##X, T1, W, N), \
52 VECT_ARRAY_VAR(vector, T1, W, N, X)); \
53 memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(result_bis_##X, T1, W, N), \
54 sizeof(VECT_VAR(result, T1, W, N)));
55
56
57 /* Overwrite "result" with the contents of "result_bis"[Y] */
58 #define TEST_EXTRA_CHUNK(T1, W, N, X,Y) \
59 memcpy(VECT_VAR(result, T1, W, N), \
60 &(VECT_VAR(result_bis_##X, T1, W, N)[Y*N]), \
61 sizeof(VECT_VAR(result, T1, W, N)));
62
63 /* With ARM RVCT, we need to declare variables before any executable
64 statement */
65 #define DECL_ALL_VLDX_DUP(X) \
66 DECL_VLDX_DUP(int, 8, 8, X); \
67 DECL_VLDX_DUP(int, 16, 4, X); \
68 DECL_VLDX_DUP(int, 32, 2, X); \
69 DECL_VLDX_DUP(int, 64, 1, X); \
70 DECL_VLDX_DUP(uint, 8, 8, X); \
71 DECL_VLDX_DUP(uint, 16, 4, X); \
72 DECL_VLDX_DUP(uint, 32, 2, X); \
73 DECL_VLDX_DUP(uint, 64, 1, X); \
74 DECL_VLDX_DUP(poly, 8, 8, X); \
75 DECL_VLDX_DUP(poly, 16, 4, X); \
76 DECL_VLDX_DUP(float, 32, 2, X)
77
78 #if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
79 #define DECL_ALL_VLDX_DUP_FP16(X) \
80 DECL_VLDX_DUP(float, 16, 4, X)
81 #endif
82
83 #define TEST_ALL_VLDX_DUP(X) \
84 TEST_VLDX_DUP(, int, s, 8, 8, X); \
85 TEST_VLDX_DUP(, int, s, 16, 4, X); \
86 TEST_VLDX_DUP(, int, s, 32, 2, X); \
87 TEST_VLDX_DUP(, int, s, 64, 1, X); \
88 TEST_VLDX_DUP(, uint, u, 8, 8, X); \
89 TEST_VLDX_DUP(, uint, u, 16, 4, X); \
90 TEST_VLDX_DUP(, uint, u, 32, 2, X); \
91 TEST_VLDX_DUP(, uint, u, 64, 1, X); \
92 TEST_VLDX_DUP(, poly, p, 8, 8, X); \
93 TEST_VLDX_DUP(, poly, p, 16, 4, X); \
94 TEST_VLDX_DUP(, float, f, 32, 2, X)
95
96 #if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
97 #define TEST_ALL_VLDX_DUP_FP16(X) \
98 TEST_VLDX_DUP(, float, f, 16, 4, X)
99 #endif
100
101 #define TEST_ALL_EXTRA_CHUNKS(X, Y) \
102 TEST_EXTRA_CHUNK(int, 8, 8, X, Y); \
103 TEST_EXTRA_CHUNK(int, 16, 4, X, Y); \
104 TEST_EXTRA_CHUNK(int, 32, 2, X, Y); \
105 TEST_EXTRA_CHUNK(int, 64, 1, X, Y); \
106 TEST_EXTRA_CHUNK(uint, 8, 8, X, Y); \
107 TEST_EXTRA_CHUNK(uint, 16, 4, X, Y); \
108 TEST_EXTRA_CHUNK(uint, 32, 2, X, Y); \
109 TEST_EXTRA_CHUNK(uint, 64, 1, X, Y); \
110 TEST_EXTRA_CHUNK(poly, 8, 8, X, Y); \
111 TEST_EXTRA_CHUNK(poly, 16, 4, X, Y); \
112 TEST_EXTRA_CHUNK(float, 32, 2, X, Y)
113
114 #if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
115 #define TEST_ALL_EXTRA_CHUNKS_FP16(X, Y) \
116 TEST_EXTRA_CHUNK(float, 16, 4, X, Y)
117 #endif
118
119
120 DECL_ALL_VLDX_DUP(2);
121 DECL_ALL_VLDX_DUP(3);
122 DECL_ALL_VLDX_DUP(4);
123 #if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
124 DECL_ALL_VLDX_DUP_FP16(2);
125 DECL_ALL_VLDX_DUP_FP16(3);
126 DECL_ALL_VLDX_DUP_FP16(4);
127 #endif
128
129 /* Check vld2_dup/vld2q_dup */
130 clean_results ();
131 #define TEST_MSG "VLD2_DUP/VLD2Q_DUP"
132 TEST_ALL_VLDX_DUP(2);
133 #if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
134 TEST_ALL_VLDX_DUP_FP16(2);
135 #endif
136 dump_results_hex2 (TEST_MSG, " chunk 0");
137 TEST_ALL_EXTRA_CHUNKS(2, 1);
138 #if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
139 TEST_ALL_EXTRA_CHUNKS_FP16(2, 1);
140 #endif
141 dump_results_hex2 (TEST_MSG, " chunk 1");
142
143 /* Check vld3_dup/vld3q_dup */
144 clean_results ();
145 #undef TEST_MSG
146 #define TEST_MSG "VLD3_DUP/VLD3Q_DUP"
147 TEST_ALL_VLDX_DUP(3);
148 #if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
149 TEST_ALL_VLDX_DUP_FP16(3);
150 #endif
151 dump_results_hex2 (TEST_MSG, " chunk 0");
152 TEST_ALL_EXTRA_CHUNKS(3, 1);
153 #if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
154 TEST_ALL_EXTRA_CHUNKS_FP16(3, 1);
155 #endif
156 dump_results_hex2 (TEST_MSG, " chunk 1");
157 TEST_ALL_EXTRA_CHUNKS(3, 2);
158 #if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
159 TEST_ALL_EXTRA_CHUNKS_FP16(3, 2);
160 #endif
161 dump_results_hex2 (TEST_MSG, " chunk 2");
162
163 /* Check vld4_dup/vld4q_dup */
164 clean_results ();
165 #undef TEST_MSG
166 #define TEST_MSG "VLD4_DUP/VLD4Q_DUP"
167 TEST_ALL_VLDX_DUP(4);
168 #if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
169 TEST_ALL_VLDX_DUP_FP16(4);
170 #endif
171 dump_results_hex2 (TEST_MSG, " chunk 0");
172 TEST_ALL_EXTRA_CHUNKS(4, 1);
173 #if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
174 TEST_ALL_EXTRA_CHUNKS_FP16(4, 1);
175 #endif
176 dump_results_hex2 (TEST_MSG, " chunk 1");
177 TEST_ALL_EXTRA_CHUNKS(4, 2);
178 #if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
179 TEST_ALL_EXTRA_CHUNKS_FP16(4, 2);
180 #endif
181 dump_results_hex2 (TEST_MSG, " chunk 2");
182 TEST_ALL_EXTRA_CHUNKS(4, 3);
183 #if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
184 TEST_ALL_EXTRA_CHUNKS_FP16(4, 3);
185 #endif
186 dump_results_hex2 (TEST_MSG, " chunk 3");
187 }
188