1 //===-- AMDGPUBaseInfo.h - Top level definitions for AMDGPU -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H 11 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H 12 13 #include "AMDKernelCodeT.h" 14 #include "llvm/IR/CallingConv.h" 15 16 namespace llvm { 17 18 class FeatureBitset; 19 class Function; 20 class GlobalValue; 21 class MCContext; 22 class MCSection; 23 class MCSubtargetInfo; 24 25 namespace AMDGPU { 26 27 struct IsaVersion { 28 unsigned Major; 29 unsigned Minor; 30 unsigned Stepping; 31 }; 32 33 IsaVersion getIsaVersion(const FeatureBitset &Features); 34 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, 35 const FeatureBitset &Features); 36 MCSection *getHSATextSection(MCContext &Ctx); 37 38 MCSection *getHSADataGlobalAgentSection(MCContext &Ctx); 39 40 MCSection *getHSADataGlobalProgramSection(MCContext &Ctx); 41 42 MCSection *getHSARodataReadonlyAgentSection(MCContext &Ctx); 43 44 bool isGroupSegment(const GlobalValue *GV); 45 bool isGlobalSegment(const GlobalValue *GV); 46 bool isReadOnlySegment(const GlobalValue *GV); 47 48 int getIntegerAttribute(const Function &F, StringRef Name, int Default); 49 50 unsigned getMaximumWorkGroupSize(const Function &F); 51 unsigned getInitialPSInputAddr(const Function &F); 52 53 bool isShader(CallingConv::ID cc); 54 bool isCompute(CallingConv::ID cc); 55 56 bool isSI(const MCSubtargetInfo &STI); 57 bool isCI(const MCSubtargetInfo &STI); 58 bool isVI(const MCSubtargetInfo &STI); 59 60 /// If \p Reg is a pseudo reg, return the correct hardware register given 61 /// \p STI otherwise return \p Reg. 62 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI); 63 64 } // end namespace AMDGPU 65 } // end namespace llvm 66 67 #endif 68