1//=-HexagonScheduleV60.td - HexagonV60 Scheduling Definitions *- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10// CVI pipes from the "Hexagon Multimedia Co-Processor Extensions Arch Spec". 11def CVI_ST : FuncUnit; 12def CVI_XLANE : FuncUnit; 13def CVI_SHIFT : FuncUnit; 14def CVI_MPY0 : FuncUnit; 15def CVI_MPY1 : FuncUnit; 16def CVI_LD : FuncUnit; 17 18// Combined functional units. 19def CVI_XLSHF : FuncUnit; 20def CVI_MPY01 : FuncUnit; 21def CVI_ALL : FuncUnit; 22 23// Combined functional unit data. 24def HexagonComboFuncsV60 : 25 ComboFuncUnits<[ 26 ComboFuncData<CVI_XLSHF , [CVI_XLANE, CVI_SHIFT]>, 27 ComboFuncData<CVI_MPY01 , [CVI_MPY0, CVI_MPY1]>, 28 ComboFuncData<CVI_ALL , [CVI_ST, CVI_XLANE, CVI_SHIFT, 29 CVI_MPY0, CVI_MPY1, CVI_LD]> 30 ]>; 31 32// Note: When adding additional vector scheduling classes, add the 33// corresponding methods to the class HexagonInstrInfo. 34def CVI_VA : InstrItinClass; 35def CVI_VA_DV : InstrItinClass; 36def CVI_VX_LONG : InstrItinClass; 37def CVI_VX_LATE : InstrItinClass; 38def CVI_VX : InstrItinClass; 39def CVI_VX_DV_LONG : InstrItinClass; 40def CVI_VX_DV : InstrItinClass; 41def CVI_VX_DV_SLOT2 : InstrItinClass; 42def CVI_VP : InstrItinClass; 43def CVI_VP_LONG : InstrItinClass; 44def CVI_VP_VS_EARLY : InstrItinClass; 45def CVI_VP_VS_LONG_EARLY : InstrItinClass; 46def CVI_VP_VS_LONG : InstrItinClass; 47def CVI_VP_VS : InstrItinClass; 48def CVI_VP_DV : InstrItinClass; 49def CVI_VS : InstrItinClass; 50def CVI_VINLANESAT : InstrItinClass; 51def CVI_VM_LD : InstrItinClass; 52def CVI_VM_TMP_LD : InstrItinClass; 53def CVI_VM_CUR_LD : InstrItinClass; 54def CVI_VM_VP_LDU : InstrItinClass; 55def CVI_VM_ST : InstrItinClass; 56def CVI_VM_NEW_ST : InstrItinClass; 57def CVI_VM_STU : InstrItinClass; 58def CVI_HIST : InstrItinClass; 59def CVI_VA_EXT : InstrItinClass; 60 61// There are four SLOTS (four parallel pipelines) in Hexagon V60 machine. 62// This file describes that machine information. 63// 64// |===========|==================================================| 65// | PIPELINE | Instruction Classes | 66// |===========|==================================================| 67// | SLOT0 | LD ST ALU32 MEMOP NV SYSTEM | 68// |-----------|--------------------------------------------------| 69// | SLOT1 | LD ST ALU32 | 70// |-----------|--------------------------------------------------| 71// | SLOT2 | XTYPE ALU32 J JR | 72// |-----------|--------------------------------------------------| 73// | SLOT3 | XTYPE ALU32 J CR | 74// |===========|==================================================| 75// 76// 77// In addition to using the above SLOTS, there are also six vector pipelines 78// in the CVI co-processor in the Hexagon V60 machine. 79// 80// |=========| |=========| |=========| |=========| |=========| |=========| 81// SLOT | CVI_LD | |CVI_MPY3 | |CVI_MPY2 | |CVI_SHIFT| |CVI_XLANE| | CVI_ST | 82// ==== |=========| |=========| |=========| |=========| |=========| |=========| 83// S0-3 | | | CVI_VA | | CVI_VA | | CVI_VA | | CVI_VA | | | 84// S2-3 | | | CVI_VX | | CVI_VX | | | | | | | 85// S0-3 | | | | | | | | | CVI_VP | | | 86// S0-3 | | | | | | | CVI_VS | | | | | 87// S0-1 |(CVI_LD) | | CVI_LD | | CVI_LD | | CVI_LD | | CVI_LD | | | 88// S0-1 |(C*TMP_LD) | | | | | | | | | | 89// S01 |(C*_LDU) | | | | | | | | C*_LDU | | | 90// S0 | | | CVI_ST | | CVI_ST | | CVI_ST | | CVI_ST | |(CVI_ST) | 91// S0 | | | | | | | | | | |(C*TMP_ST) 92// S01 | | | | | | | | | VSTU | |(C*_STU) | 93// |=========| |=========| |=========| |=========| |=========| |=========| 94// |=====================| |=====================| 95// | CVI_MPY2 & CVI_MPY3 | |CVI_XLANE & CVI_SHIFT| 96// |=====================| |=====================| 97// S0-3 | CVI_VA_DV | | CVI_VA_DV | 98// S0-3 | | | CVI_VP_DV | 99// S2-3 | CVI_VX_DV | | | 100// |=====================| |=====================| 101// |=====================================================================| 102// S0-3 | CVI_HIST Histogram | 103// S0123| CVI_VA_EXT Extract | 104// |=====================================================================| 105 106def HexagonItinerariesV60 : 107 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP, 108 CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1, 109 CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL], [], [ 110 // ALU32 111 InstrItinData<ALU32_2op_tc_1_SLOT0123 , 112 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 113 InstrItinData<ALU32_2op_tc_2early_SLOT0123, 114 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 115 InstrItinData<ALU32_3op_tc_1_SLOT0123 , 116 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 117 InstrItinData<ALU32_3op_tc_2_SLOT0123 , 118 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 119 InstrItinData<ALU32_3op_tc_2early_SLOT0123, 120 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 121 InstrItinData<ALU32_ADDI_tc_1_SLOT0123 , 122 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 123 124 // ALU64 125 InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 126 InstrItinData<ALU64_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>, 127 InstrItinData<ALU64_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>, 128 InstrItinData<ALU64_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>, 129 130 // CR -> System 131 InstrItinData<CR_tc_2_SLOT3 , [InstrStage<2, [SLOT3]>]>, 132 InstrItinData<CR_tc_2early_SLOT3 , [InstrStage<2, [SLOT3]>]>, 133 InstrItinData<CR_tc_3x_SLOT3 , [InstrStage<3, [SLOT3]>]>, 134 135 // Jump (conditional/unconditional/return etc) 136 InstrItinData<CR_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>, 137 InstrItinData<CR_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>, 138 InstrItinData<CJ_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 139 InstrItinData<CJ_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>, 140 InstrItinData<J_tc_2early_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>, 141 InstrItinData<J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT , [InstrStage<1, [SLOT2, SLOT3]>]>, 142 143 // JR 144 InstrItinData<J_tc_2early_SLOT2 , [InstrStage<2, [SLOT2]>]>, 145 InstrItinData<J_tc_3stall_SLOT2 , [InstrStage<3, [SLOT2]>]>, 146 147 // Extender 148 InstrItinData<EXTENDER_tc_1_SLOT0123, [InstrStage<1, 149 [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 150 151 // Load 152 InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>, 153 InstrItinData<LD_tc_3or4stall_SLOT0, [InstrStage<4, [SLOT0]>]>, 154 InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>, 155 156 // M 157 InstrItinData<M_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 158 InstrItinData<M_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>, 159 InstrItinData<M_tc_3_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>, 160 InstrItinData<M_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>, 161 InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<4, [SLOT2, SLOT3]>]>, 162 InstrItinData<M_tc_3stall_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>, 163 164 // Store 165 InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, 166 InstrItinData<ST_tc_3stall_SLOT0, [InstrStage<3, [SLOT0]>]>, 167 InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>, 168 InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>, 169 170 // Subinsn 171 InstrItinData<SUBINSN_tc_2early_SLOT0, [InstrStage<2, [SLOT0]>]>, 172 InstrItinData<SUBINSN_tc_3stall_SLOT0, [InstrStage<3, [SLOT0]>]>, 173 InstrItinData<SUBINSN_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>, 174 InstrItinData<SUBINSN_tc_1_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, 175 InstrItinData<SUBINSN_tc_2early_SLOT01, 176 [InstrStage<2, [SLOT0, SLOT1]>]>, 177 InstrItinData<SUBINSN_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>, 178 InstrItinData<SUBINSN_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, 179 180 // S 181 InstrItinData<S_2op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 182 InstrItinData<S_2op_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>, 183 InstrItinData<S_2op_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>, 184 // The S_2op_tc_3x_SLOT23 slots are 4 cycles on v60. 185 InstrItinData<S_2op_tc_3or4x_SLOT23 , [InstrStage<4, [SLOT2, SLOT3]>]>, 186 InstrItinData<S_3op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 187 InstrItinData<S_3op_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>, 188 InstrItinData<S_3op_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>, 189 InstrItinData<S_3op_tc_3_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>, 190 InstrItinData<S_3op_tc_3stall_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>, 191 InstrItinData<S_3op_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>, 192 193 // New Value Compare Jump 194 InstrItinData<NCJ_tc_3or4stall_SLOT0, [InstrStage<4, [SLOT0]>]>, 195 196 // Mem ops 197 InstrItinData<V2LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>, 198 InstrItinData<V2LDST_tc_ld_SLOT01 , [InstrStage<2, [SLOT0, SLOT1]>]>, 199 InstrItinData<V2LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, 200 InstrItinData<V4LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>, 201 InstrItinData<V4LDST_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>, 202 InstrItinData<V4LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, 203 204 // Endloop 205 InstrItinData<J_tc_2early_SLOT0123, [InstrStage<2, [SLOT_ENDLOOP]>]>, 206 207 // Vector 208 InstrItinData<COPROC_VMEM_vtc_long_SLOT01, 209 [InstrStage<3, [SLOT0, SLOT1]>]>, 210 InstrItinData<COPROC_VX_vtc_long_SLOT23 , 211 [InstrStage<3, [SLOT2, SLOT3]>]>, 212 InstrItinData<COPROC_VX_vtc_SLOT23 , 213 [InstrStage<3, [SLOT2, SLOT3]>]>, 214 InstrItinData<MAPPING_tc_1_SLOT0123 , 215 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 216 217 // Duplex and Compound 218 InstrItinData<DUPLEX , [InstrStage<1, [SLOT0]>]>, 219 InstrItinData<COMPOUND_CJ_ARCHDEPSLOT , [InstrStage<1, [SLOT2, SLOT3]>]>, 220 InstrItinData<COMPOUND , [InstrStage<1, [SLOT2, SLOT3]>]>, 221 // Misc 222 InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 223 InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 224 InstrItinData<PSEUDOM , [InstrStage<1, [SLOT2, SLOT3], 0>, 225 InstrStage<1, [SLOT2, SLOT3]>]>, 226 227 // Latest CVI spec definitions. 228 InstrItinData<CVI_VA,[InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>, 229 InstrStage<1, [CVI_XLANE,CVI_SHIFT, 230 CVI_MPY0, CVI_MPY1]>]>, 231 InstrItinData<CVI_VA_DV, 232 [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>, 233 InstrStage<1, [CVI_XLSHF, CVI_MPY01]>]>, 234 InstrItinData<CVI_VX_LONG, [InstrStage<1, [SLOT2, SLOT3], 0>, 235 InstrStage<1, [CVI_MPY0, CVI_MPY1]>]>, 236 InstrItinData<CVI_VX_LATE, [InstrStage<1, [SLOT2, SLOT3], 0>, 237 InstrStage<1, [CVI_MPY0, CVI_MPY1]>]>, 238 InstrItinData<CVI_VX,[InstrStage<1, [SLOT2, SLOT3], 0>, 239 InstrStage<1, [CVI_MPY0, CVI_MPY1]>]>, 240 InstrItinData<CVI_VX_DV_LONG, 241 [InstrStage<1, [SLOT2, SLOT3], 0>, 242 InstrStage<1, [CVI_MPY01]>]>, 243 InstrItinData<CVI_VX_DV, 244 [InstrStage<1, [SLOT2, SLOT3], 0>, 245 InstrStage<1, [CVI_MPY01]>]>, 246 InstrItinData<CVI_VX_DV_SLOT2, 247 [InstrStage<1, [SLOT2], 0>, 248 InstrStage<1, [CVI_MPY01]>]>, 249 InstrItinData<CVI_VP, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>, 250 InstrStage<1, [CVI_XLANE]>]>, 251 InstrItinData<CVI_VP_LONG, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>, 252 InstrStage<1, [CVI_XLANE]>]>, 253 InstrItinData<CVI_VP_VS_EARLY, 254 [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>, 255 InstrStage<1, [CVI_XLSHF]>]>, 256 InstrItinData<CVI_VP_VS_LONG, 257 [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>, 258 InstrStage<1, [CVI_XLSHF]>]>, 259 InstrItinData<CVI_VP_VS, 260 [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>, 261 InstrStage<1, [CVI_XLSHF]>]>, 262 InstrItinData<CVI_VP_VS_LONG_EARLY, 263 [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>, 264 InstrStage<1, [CVI_XLSHF]>]>, 265 InstrItinData<CVI_VP_DV , [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>, 266 InstrStage<1, [CVI_XLSHF]>]>, 267 InstrItinData<CVI_VS, 268 [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>, 269 InstrStage<1, [CVI_SHIFT]>]>, 270 InstrItinData<CVI_VINLANESAT, 271 [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>, 272 InstrStage<1, [CVI_SHIFT]>]>, 273 InstrItinData<CVI_VM_LD , [InstrStage<1, [SLOT0, SLOT1], 0>, 274 InstrStage<1, [CVI_LD], 0>, 275 InstrStage<1, [CVI_XLANE, CVI_SHIFT, 276 CVI_MPY0, CVI_MPY1]>]>, 277 InstrItinData<CVI_VM_TMP_LD,[InstrStage<1,[SLOT0, SLOT1], 0>, 278 InstrStage<1, [CVI_LD]>]>, 279 InstrItinData<CVI_VM_CUR_LD,[InstrStage<1,[SLOT0, SLOT1], 0>, 280 InstrStage<1, [CVI_LD], 0>, 281 InstrStage<1, [CVI_XLANE, CVI_SHIFT, 282 CVI_MPY0, CVI_MPY1]>]>, 283 InstrItinData<CVI_VM_VP_LDU,[InstrStage<1,[SLOT0], 0>, 284 InstrStage<1, [SLOT1], 0>, 285 InstrStage<1, [CVI_LD], 0>, 286 InstrStage<1, [CVI_XLANE]>]>, 287 InstrItinData<CVI_VM_ST , [InstrStage<1, [SLOT0], 0>, 288 InstrStage<1, [CVI_ST], 0>, 289 InstrStage<1, [CVI_XLANE, CVI_SHIFT, 290 CVI_MPY0, CVI_MPY1]>]>, 291 InstrItinData<CVI_VM_NEW_ST,[InstrStage<1,[SLOT0], 0>, 292 InstrStage<1, [CVI_ST]>]>, 293 InstrItinData<CVI_VM_STU , [InstrStage<1, [SLOT0], 0>, 294 InstrStage<1, [SLOT1], 0>, 295 InstrStage<1, [CVI_ST], 0>, 296 InstrStage<1, [CVI_XLANE]>]>, 297 InstrItinData<CVI_HIST , [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>, 298 InstrStage<1, [CVI_ALL]>]> 299 ]>; 300 301def HexagonModelV60 : SchedMachineModel { 302 // Max issue per cycle == bundle width. 303 let IssueWidth = 4; 304 let Itineraries = HexagonItinerariesV60; 305 let LoadLatency = 1; 306 let CompleteModel = 0; 307} 308 309//===----------------------------------------------------------------------===// 310// Hexagon V60 Resource Definitions - 311//===----------------------------------------------------------------------===// 312