1 //===- NVPTXInstrInfo.h - NVPTX Instruction Information----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the niversity of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the NVPTX implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTXINSTRINFO_H 15 #define LLVM_LIB_TARGET_NVPTX_NVPTXINSTRINFO_H 16 17 #include "NVPTX.h" 18 #include "NVPTXRegisterInfo.h" 19 #include "llvm/Target/TargetInstrInfo.h" 20 21 #define GET_INSTRINFO_HEADER 22 #include "NVPTXGenInstrInfo.inc" 23 24 namespace llvm { 25 26 class NVPTXInstrInfo : public NVPTXGenInstrInfo { 27 const NVPTXRegisterInfo RegInfo; 28 virtual void anchor(); 29 public: 30 explicit NVPTXInstrInfo(); 31 getRegisterInfo()32 const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; } 33 34 /* The following virtual functions are used in register allocation. 35 * They are not implemented because the existing interface and the logic 36 * at the caller side do not work for the elementized vector load and store. 37 * 38 * virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 39 * int &FrameIndex) const; 40 * virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 41 * int &FrameIndex) const; 42 * virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 43 * MachineBasicBlock::iterator MBBI, 44 * unsigned SrcReg, bool isKill, int FrameIndex, 45 * const TargetRegisterClass *RC) const; 46 * virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 47 * MachineBasicBlock::iterator MBBI, 48 * unsigned DestReg, int FrameIndex, 49 * const TargetRegisterClass *RC) const; 50 */ 51 52 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 53 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, 54 bool KillSrc) const override; 55 virtual bool isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, 56 unsigned &DestReg) const; 57 bool isLoadInstr(const MachineInstr &MI, unsigned &AddrSpace) const; 58 bool isStoreInstr(const MachineInstr &MI, unsigned &AddrSpace) const; 59 60 virtual bool CanTailMerge(const MachineInstr *MI) const; 61 // Branch analysis. 62 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 63 MachineBasicBlock *&FBB, 64 SmallVectorImpl<MachineOperand> &Cond, 65 bool AllowModify) const override; 66 unsigned RemoveBranch(MachineBasicBlock &MBB) const override; 67 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 68 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 69 const DebugLoc &DL) const override; getLdStCodeAddrSpace(const MachineInstr & MI)70 unsigned getLdStCodeAddrSpace(const MachineInstr &MI) const { 71 return MI.getOperand(2).getImm(); 72 } 73 74 }; 75 76 } // namespace llvm 77 78 #endif 79