1//===-- SparcInstr64Bit.td - 64-bit instructions for Sparc Target ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains instruction definitions and patterns needed for 64-bit 11// code generation on SPARC v9. 12// 13// Some SPARC v9 instructions are defined in SparcInstrInfo.td because they can 14// also be used in 32-bit code running on a SPARC v9 CPU. 15// 16//===----------------------------------------------------------------------===// 17 18let Predicates = [Is64Bit] in { 19// The same integer registers are used for i32 and i64 values. 20// When registers hold i32 values, the high bits are don't care. 21// This give us free trunc and anyext. 22def : Pat<(i64 (anyext i32:$val)), (COPY_TO_REGCLASS $val, I64Regs)>; 23def : Pat<(i32 (trunc i64:$val)), (COPY_TO_REGCLASS $val, IntRegs)>; 24 25} // Predicates = [Is64Bit] 26 27 28//===----------------------------------------------------------------------===// 29// 64-bit Shift Instructions. 30//===----------------------------------------------------------------------===// 31// 32// The 32-bit shift instructions are still available. The left shift srl 33// instructions shift all 64 bits, but it only accepts a 5-bit shift amount. 34// 35// The srl instructions only shift the low 32 bits and clear the high 32 bits. 36// Finally, sra shifts the low 32 bits and sign-extends to 64 bits. 37 38let Predicates = [Is64Bit] in { 39 40def : Pat<(i64 (zext i32:$val)), (SRLri $val, 0)>; 41def : Pat<(i64 (sext i32:$val)), (SRAri $val, 0)>; 42 43def : Pat<(i64 (and i64:$val, 0xffffffff)), (SRLri $val, 0)>; 44def : Pat<(i64 (sext_inreg i64:$val, i32)), (SRAri $val, 0)>; 45 46defm SLLX : F3_S<"sllx", 0b100101, 1, shl, i64, I64Regs>; 47defm SRLX : F3_S<"srlx", 0b100110, 1, srl, i64, I64Regs>; 48defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, I64Regs>; 49 50} // Predicates = [Is64Bit] 51 52 53//===----------------------------------------------------------------------===// 54// 64-bit Immediates. 55//===----------------------------------------------------------------------===// 56// 57// All 32-bit immediates can be materialized with sethi+or, but 64-bit 58// immediates may require more code. There may be a point where it is 59// preferable to use a constant pool load instead, depending on the 60// microarchitecture. 61 62// Single-instruction patterns. 63 64// The ALU instructions want their simm13 operands as i32 immediates. 65def as_i32imm : SDNodeXForm<imm, [{ 66 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32); 67}]>; 68def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>; 69def : Pat<(i64 SETHIimm:$val), (SETHIi (HI22 $val))>; 70 71// Double-instruction patterns. 72 73// All unsigned i32 immediates can be handled by sethi+or. 74def uimm32 : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>; 75def : Pat<(i64 uimm32:$val), (ORri (SETHIi (HI22 $val)), (LO10 $val))>, 76 Requires<[Is64Bit]>; 77 78// All negative i33 immediates can be handled by sethi+xor. 79def nimm33 : PatLeaf<(imm), [{ 80 int64_t Imm = N->getSExtValue(); 81 return Imm < 0 && isInt<33>(Imm); 82}]>; 83// Bits 10-31 inverted. Same as assembler's %hix. 84def HIX22 : SDNodeXForm<imm, [{ 85 uint64_t Val = (~N->getZExtValue() >> 10) & ((1u << 22) - 1); 86 return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32); 87}]>; 88// Bits 0-9 with ones in bits 10-31. Same as assembler's %lox. 89def LOX10 : SDNodeXForm<imm, [{ 90 return CurDAG->getTargetConstant(~(~N->getZExtValue() & 0x3ff), SDLoc(N), 91 MVT::i32); 92}]>; 93def : Pat<(i64 nimm33:$val), (XORri (SETHIi (HIX22 $val)), (LOX10 $val))>, 94 Requires<[Is64Bit]>; 95 96// More possible patterns: 97// 98// (sllx sethi, n) 99// (sllx simm13, n) 100// 101// 3 instrs: 102// 103// (xor (sllx sethi), simm13) 104// (sllx (xor sethi, simm13)) 105// 106// 4 instrs: 107// 108// (or sethi, (sllx sethi)) 109// (xnor sethi, (sllx sethi)) 110// 111// 5 instrs: 112// 113// (or (sllx sethi), (or sethi, simm13)) 114// (xnor (sllx sethi), (or sethi, simm13)) 115// (or (sllx sethi), (sllx sethi)) 116// (xnor (sllx sethi), (sllx sethi)) 117// 118// Worst case is 6 instrs: 119// 120// (or (sllx (or sethi, simmm13)), (or sethi, simm13)) 121 122// Bits 42-63, same as assembler's %hh. 123def HH22 : SDNodeXForm<imm, [{ 124 uint64_t Val = (N->getZExtValue() >> 42) & ((1u << 22) - 1); 125 return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32); 126}]>; 127// Bits 32-41, same as assembler's %hm. 128def HM10 : SDNodeXForm<imm, [{ 129 uint64_t Val = (N->getZExtValue() >> 32) & ((1u << 10) - 1); 130 return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32); 131}]>; 132def : Pat<(i64 imm:$val), 133 (ORrr (SLLXri (ORri (SETHIi (HH22 $val)), (HM10 $val)), (i32 32)), 134 (ORri (SETHIi (HI22 $val)), (LO10 $val)))>, 135 Requires<[Is64Bit]>; 136 137 138//===----------------------------------------------------------------------===// 139// 64-bit Integer Arithmetic and Logic. 140//===----------------------------------------------------------------------===// 141 142let Predicates = [Is64Bit] in { 143 144// Register-register instructions. 145let isCodeGenOnly = 1 in { 146defm ANDX : F3_12<"and", 0b000001, and, I64Regs, i64, i64imm>; 147defm ORX : F3_12<"or", 0b000010, or, I64Regs, i64, i64imm>; 148defm XORX : F3_12<"xor", 0b000011, xor, I64Regs, i64, i64imm>; 149 150def ANDXNrr : F3_1<2, 0b000101, 151 (outs I64Regs:$dst), (ins I64Regs:$b, I64Regs:$c), 152 "andn $b, $c, $dst", 153 [(set i64:$dst, (and i64:$b, (not i64:$c)))]>; 154def ORXNrr : F3_1<2, 0b000110, 155 (outs I64Regs:$dst), (ins I64Regs:$b, I64Regs:$c), 156 "orn $b, $c, $dst", 157 [(set i64:$dst, (or i64:$b, (not i64:$c)))]>; 158def XNORXrr : F3_1<2, 0b000111, 159 (outs I64Regs:$dst), (ins I64Regs:$b, I64Regs:$c), 160 "xnor $b, $c, $dst", 161 [(set i64:$dst, (not (xor i64:$b, i64:$c)))]>; 162 163defm ADDX : F3_12<"add", 0b000000, add, I64Regs, i64, i64imm>; 164defm SUBX : F3_12<"sub", 0b000100, sub, I64Regs, i64, i64imm>; 165 166def TLS_ADDXrr : F3_1<2, 0b000000, (outs I64Regs:$rd), 167 (ins I64Regs:$rs1, I64Regs:$rs2, TLSSym:$sym), 168 "add $rs1, $rs2, $rd, $sym", 169 [(set i64:$rd, 170 (tlsadd i64:$rs1, i64:$rs2, tglobaltlsaddr:$sym))]>; 171 172// "LEA" form of add 173def LEAX_ADDri : F3_2<2, 0b000000, 174 (outs I64Regs:$dst), (ins MEMri:$addr), 175 "add ${addr:arith}, $dst", 176 [(set iPTR:$dst, ADDRri:$addr)]>; 177} 178 179def : Pat<(SPcmpicc i64:$a, i64:$b), (CMPrr $a, $b)>; 180def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>; 181def : Pat<(ctpop i64:$src), (POPCrr $src)>; 182 183} // Predicates = [Is64Bit] 184 185 186//===----------------------------------------------------------------------===// 187// 64-bit Integer Multiply and Divide. 188//===----------------------------------------------------------------------===// 189 190let Predicates = [Is64Bit] in { 191 192def MULXrr : F3_1<2, 0b001001, 193 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), 194 "mulx $rs1, $rs2, $rd", 195 [(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>; 196def MULXri : F3_2<2, 0b001001, 197 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), 198 "mulx $rs1, $simm13, $rd", 199 [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>; 200 201// Division can trap. 202let hasSideEffects = 1 in { 203def SDIVXrr : F3_1<2, 0b101101, 204 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), 205 "sdivx $rs1, $rs2, $rd", 206 [(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>; 207def SDIVXri : F3_2<2, 0b101101, 208 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), 209 "sdivx $rs1, $simm13, $rd", 210 [(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$simm13)))]>; 211 212def UDIVXrr : F3_1<2, 0b001101, 213 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), 214 "udivx $rs1, $rs2, $rd", 215 [(set i64:$rd, (udiv i64:$rs1, i64:$rs2))]>; 216def UDIVXri : F3_2<2, 0b001101, 217 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), 218 "udivx $rs1, $simm13, $rd", 219 [(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$simm13)))]>; 220} // hasSideEffects = 1 221 222} // Predicates = [Is64Bit] 223 224 225//===----------------------------------------------------------------------===// 226// 64-bit Loads and Stores. 227//===----------------------------------------------------------------------===// 228// 229// All the 32-bit loads and stores are available. The extending loads are sign 230// or zero-extending to 64 bits. The LDrr and LDri instructions load 32 bits 231// zero-extended to i64. Their mnemonic is lduw in SPARC v9 (Load Unsigned 232// Word). 233// 234// SPARC v9 adds 64-bit loads as well as a sign-extending ldsw i32 loads. 235 236let Predicates = [Is64Bit] in { 237 238// 64-bit loads. 239let DecoderMethod = "DecodeLoadInt" in 240 defm LDX : Load<"ldx", 0b001011, load, I64Regs, i64>; 241 242let mayLoad = 1, isCodeGenOnly = 1, isAsmParserOnly = 1 in 243 def TLS_LDXrr : F3_1<3, 0b001011, 244 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym), 245 "ldx [$addr], $dst, $sym", 246 [(set i64:$dst, 247 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>; 248 249// Extending loads to i64. 250def : Pat<(i64 (zextloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; 251def : Pat<(i64 (zextloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; 252def : Pat<(i64 (extloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; 253def : Pat<(i64 (extloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; 254 255def : Pat<(i64 (zextloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; 256def : Pat<(i64 (zextloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; 257def : Pat<(i64 (extloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; 258def : Pat<(i64 (extloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; 259def : Pat<(i64 (sextloadi8 ADDRrr:$addr)), (LDSBrr ADDRrr:$addr)>; 260def : Pat<(i64 (sextloadi8 ADDRri:$addr)), (LDSBri ADDRri:$addr)>; 261 262def : Pat<(i64 (zextloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>; 263def : Pat<(i64 (zextloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>; 264def : Pat<(i64 (extloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>; 265def : Pat<(i64 (extloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>; 266def : Pat<(i64 (sextloadi16 ADDRrr:$addr)), (LDSHrr ADDRrr:$addr)>; 267def : Pat<(i64 (sextloadi16 ADDRri:$addr)), (LDSHri ADDRri:$addr)>; 268 269def : Pat<(i64 (zextloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>; 270def : Pat<(i64 (zextloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>; 271def : Pat<(i64 (extloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>; 272def : Pat<(i64 (extloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>; 273 274// Sign-extending load of i32 into i64 is a new SPARC v9 instruction. 275let DecoderMethod = "DecodeLoadInt" in 276 defm LDSW : Load<"ldsw", 0b001000, sextloadi32, I64Regs, i64>; 277 278// 64-bit stores. 279let DecoderMethod = "DecodeStoreInt" in 280 defm STX : Store<"stx", 0b001110, store, I64Regs, i64>; 281 282// Truncating stores from i64 are identical to the i32 stores. 283def : Pat<(truncstorei8 i64:$src, ADDRrr:$addr), (STBrr ADDRrr:$addr, $src)>; 284def : Pat<(truncstorei8 i64:$src, ADDRri:$addr), (STBri ADDRri:$addr, $src)>; 285def : Pat<(truncstorei16 i64:$src, ADDRrr:$addr), (STHrr ADDRrr:$addr, $src)>; 286def : Pat<(truncstorei16 i64:$src, ADDRri:$addr), (STHri ADDRri:$addr, $src)>; 287def : Pat<(truncstorei32 i64:$src, ADDRrr:$addr), (STrr ADDRrr:$addr, $src)>; 288def : Pat<(truncstorei32 i64:$src, ADDRri:$addr), (STri ADDRri:$addr, $src)>; 289 290// store 0, addr -> store %g0, addr 291def : Pat<(store (i64 0), ADDRrr:$dst), (STXrr ADDRrr:$dst, (i64 G0))>; 292def : Pat<(store (i64 0), ADDRri:$dst), (STXri ADDRri:$dst, (i64 G0))>; 293 294} // Predicates = [Is64Bit] 295 296 297//===----------------------------------------------------------------------===// 298// 64-bit Conditionals. 299//===----------------------------------------------------------------------===// 300 301// 302// Flag-setting instructions like subcc and addcc set both icc and xcc flags. 303// The icc flags correspond to the 32-bit result, and the xcc are for the 304// full 64-bit result. 305// 306// We reuse CMPICC SDNodes for compares, but use new BRXCC branch nodes for 307// 64-bit compares. See LowerBR_CC. 308 309let Predicates = [Is64Bit] in { 310 311let Uses = [ICC], cc = 0b10 in 312 defm BPX : IPredBranch<"%xcc", [(SPbrxcc bb:$imm19, imm:$cond)]>; 313 314// Conditional moves on %xcc. 315let Uses = [ICC], Constraints = "$f = $rd" in { 316let intcc = 1, cc = 0b10 in { 317def MOVXCCrr : F4_1<0b101100, (outs IntRegs:$rd), 318 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond), 319 "mov$cond %xcc, $rs2, $rd", 320 [(set i32:$rd, 321 (SPselectxcc i32:$rs2, i32:$f, imm:$cond))]>; 322def MOVXCCri : F4_2<0b101100, (outs IntRegs:$rd), 323 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond), 324 "mov$cond %xcc, $simm11, $rd", 325 [(set i32:$rd, 326 (SPselectxcc simm11:$simm11, i32:$f, imm:$cond))]>; 327} // cc 328 329let intcc = 1, opf_cc = 0b10 in { 330def FMOVS_XCC : F4_3<0b110101, 0b000001, (outs FPRegs:$rd), 331 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond), 332 "fmovs$cond %xcc, $rs2, $rd", 333 [(set f32:$rd, 334 (SPselectxcc f32:$rs2, f32:$f, imm:$cond))]>; 335def FMOVD_XCC : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd), 336 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond), 337 "fmovd$cond %xcc, $rs2, $rd", 338 [(set f64:$rd, 339 (SPselectxcc f64:$rs2, f64:$f, imm:$cond))]>; 340def FMOVQ_XCC : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd), 341 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond), 342 "fmovq$cond %xcc, $rs2, $rd", 343 [(set f128:$rd, 344 (SPselectxcc f128:$rs2, f128:$f, imm:$cond))]>; 345} // opf_cc 346} // Uses, Constraints 347 348// Branch On integer register with Prediction (BPr). 349let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in 350multiclass BranchOnReg<bits<3> cond, string OpcStr> { 351 def napt : F2_4<cond, 0, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16), 352 !strconcat(OpcStr, " $rs1, $imm16"), []>; 353 def apt : F2_4<cond, 1, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16), 354 !strconcat(OpcStr, ",a $rs1, $imm16"), []>; 355 def napn : F2_4<cond, 0, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16), 356 !strconcat(OpcStr, ",pn $rs1, $imm16"), []>; 357 def apn : F2_4<cond, 1, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16), 358 !strconcat(OpcStr, ",a,pn $rs1, $imm16"), []>; 359} 360 361multiclass bpr_alias<string OpcStr, Instruction NAPT, Instruction APT> { 362 def : InstAlias<!strconcat(OpcStr, ",pt $rs1, $imm16"), 363 (NAPT I64Regs:$rs1, bprtarget16:$imm16), 0>; 364 def : InstAlias<!strconcat(OpcStr, ",a,pt $rs1, $imm16"), 365 (APT I64Regs:$rs1, bprtarget16:$imm16), 0>; 366} 367 368defm BPZ : BranchOnReg<0b001, "brz">; 369defm BPLEZ : BranchOnReg<0b010, "brlez">; 370defm BPLZ : BranchOnReg<0b011, "brlz">; 371defm BPNZ : BranchOnReg<0b101, "brnz">; 372defm BPGZ : BranchOnReg<0b110, "brgz">; 373defm BPGEZ : BranchOnReg<0b111, "brgez">; 374 375defm : bpr_alias<"brz", BPZnapt, BPZapt >; 376defm : bpr_alias<"brlez", BPLEZnapt, BPLEZapt>; 377defm : bpr_alias<"brlz", BPLZnapt, BPLZapt >; 378defm : bpr_alias<"brnz", BPNZnapt, BPNZapt >; 379defm : bpr_alias<"brgz", BPGZnapt, BPGZapt >; 380defm : bpr_alias<"brgez", BPGEZnapt, BPGEZapt>; 381 382// Move integer register on register condition (MOVr). 383multiclass MOVR< bits<3> rcond, string OpcStr> { 384 def rr : F4_4r<0b101111, 0b00000, rcond, (outs I64Regs:$rd), 385 (ins I64Regs:$rs1, IntRegs:$rs2), 386 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>; 387 388 def ri : F4_4i<0b101111, rcond, (outs I64Regs:$rd), 389 (ins I64Regs:$rs1, i64imm:$simm10), 390 !strconcat(OpcStr, " $rs1, $simm10, $rd"), []>; 391} 392 393defm MOVRRZ : MOVR<0b001, "movrz">; 394defm MOVRLEZ : MOVR<0b010, "movrlez">; 395defm MOVRLZ : MOVR<0b011, "movrlz">; 396defm MOVRNZ : MOVR<0b101, "movrnz">; 397defm MOVRGZ : MOVR<0b110, "movrgz">; 398defm MOVRGEZ : MOVR<0b111, "movrgez">; 399 400// Move FP register on integer register condition (FMOVr). 401multiclass FMOVR<bits<3> rcond, string OpcStr> { 402 403 def S : F4_4r<0b110101, 0b00101, rcond, 404 (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2), 405 !strconcat(!strconcat("fmovrs", OpcStr)," $rs1, $rs2, $rd"), 406 []>; 407 def D : F4_4r<0b110101, 0b00110, rcond, 408 (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2), 409 !strconcat(!strconcat("fmovrd", OpcStr)," $rs1, $rs2, $rd"), 410 []>; 411 def Q : F4_4r<0b110101, 0b00111, rcond, 412 (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2), 413 !strconcat(!strconcat("fmovrq", OpcStr)," $rs1, $rs2, $rd"), 414 []>, Requires<[HasHardQuad]>; 415} 416 417let Predicates = [HasV9] in { 418 defm FMOVRZ : FMOVR<0b001, "z">; 419 defm FMOVRLEZ : FMOVR<0b010, "lez">; 420 defm FMOVRLZ : FMOVR<0b011, "lz">; 421 defm FMOVRNZ : FMOVR<0b101, "nz">; 422 defm FMOVRGZ : FMOVR<0b110, "gz">; 423 defm FMOVRGEZ : FMOVR<0b111, "gez">; 424} 425 426//===----------------------------------------------------------------------===// 427// 64-bit Floating Point Conversions. 428//===----------------------------------------------------------------------===// 429 430let Predicates = [Is64Bit] in { 431 432def FXTOS : F3_3u<2, 0b110100, 0b010000100, 433 (outs FPRegs:$rd), (ins DFPRegs:$rs2), 434 "fxtos $rs2, $rd", 435 [(set FPRegs:$rd, (SPxtof DFPRegs:$rs2))]>; 436def FXTOD : F3_3u<2, 0b110100, 0b010001000, 437 (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 438 "fxtod $rs2, $rd", 439 [(set DFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>; 440def FXTOQ : F3_3u<2, 0b110100, 0b010001100, 441 (outs QFPRegs:$rd), (ins DFPRegs:$rs2), 442 "fxtoq $rs2, $rd", 443 [(set QFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>, 444 Requires<[HasHardQuad]>; 445 446def FSTOX : F3_3u<2, 0b110100, 0b010000001, 447 (outs DFPRegs:$rd), (ins FPRegs:$rs2), 448 "fstox $rs2, $rd", 449 [(set DFPRegs:$rd, (SPftox FPRegs:$rs2))]>; 450def FDTOX : F3_3u<2, 0b110100, 0b010000010, 451 (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 452 "fdtox $rs2, $rd", 453 [(set DFPRegs:$rd, (SPftox DFPRegs:$rs2))]>; 454def FQTOX : F3_3u<2, 0b110100, 0b010000011, 455 (outs DFPRegs:$rd), (ins QFPRegs:$rs2), 456 "fqtox $rs2, $rd", 457 [(set DFPRegs:$rd, (SPftox QFPRegs:$rs2))]>, 458 Requires<[HasHardQuad]>; 459 460} // Predicates = [Is64Bit] 461 462def : Pat<(SPselectxcc i64:$t, i64:$f, imm:$cond), 463 (MOVXCCrr $t, $f, imm:$cond)>; 464def : Pat<(SPselectxcc (i64 simm11:$t), i64:$f, imm:$cond), 465 (MOVXCCri (as_i32imm $t), $f, imm:$cond)>; 466 467def : Pat<(SPselecticc i64:$t, i64:$f, imm:$cond), 468 (MOVICCrr $t, $f, imm:$cond)>; 469def : Pat<(SPselecticc (i64 simm11:$t), i64:$f, imm:$cond), 470 (MOVICCri (as_i32imm $t), $f, imm:$cond)>; 471 472def : Pat<(SPselectfcc i64:$t, i64:$f, imm:$cond), 473 (MOVFCCrr $t, $f, imm:$cond)>; 474def : Pat<(SPselectfcc (i64 simm11:$t), i64:$f, imm:$cond), 475 (MOVFCCri (as_i32imm $t), $f, imm:$cond)>; 476 477} // Predicates = [Is64Bit] 478 479 480// 64 bit SETHI 481let Predicates = [Is64Bit], isCodeGenOnly = 1 in { 482def SETHIXi : F2_1<0b100, 483 (outs IntRegs:$rd), (ins i64imm:$imm22), 484 "sethi $imm22, $rd", 485 [(set i64:$rd, SETHIimm:$imm22)]>; 486} 487 488// ATOMICS. 489let Predicates = [Is64Bit], Constraints = "$swap = $rd", asi = 0b10000000 in { 490 def CASXrr: F3_1_asi<3, 0b111110, 491 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2, 492 I64Regs:$swap), 493 "casx [$rs1], $rs2, $rd", 494 [(set i64:$rd, 495 (atomic_cmp_swap_64 i64:$rs1, i64:$rs2, i64:$swap))]>; 496 497} // Predicates = [Is64Bit], Constraints = ... 498 499let Predicates = [Is64Bit] in { 500 501def : Pat<(atomic_fence imm, imm), (MEMBARi 0xf)>; 502 503// atomic_load_64 addr -> load addr 504def : Pat<(i64 (atomic_load_64 ADDRrr:$src)), (LDXrr ADDRrr:$src)>; 505def : Pat<(i64 (atomic_load_64 ADDRri:$src)), (LDXri ADDRri:$src)>; 506 507// atomic_store_64 val, addr -> store val, addr 508def : Pat<(atomic_store_64 ADDRrr:$dst, i64:$val), (STXrr ADDRrr:$dst, $val)>; 509def : Pat<(atomic_store_64 ADDRri:$dst, i64:$val), (STXri ADDRri:$dst, $val)>; 510 511} // Predicates = [Is64Bit] 512 513let Predicates = [Is64Bit], hasSideEffects = 1, Uses = [ICC], cc = 0b10 in 514 defm TXCC : TRAP<"%xcc">; 515 516// Global addresses, constant pool entries 517let Predicates = [Is64Bit] in { 518 519def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 520def : Pat<(SPlo tglobaladdr:$in), (ORXri (i64 G0), tglobaladdr:$in)>; 521def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 522def : Pat<(SPlo tconstpool:$in), (ORXri (i64 G0), tconstpool:$in)>; 523 524// GlobalTLS addresses 525def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>; 526def : Pat<(SPlo tglobaltlsaddr:$in), (ORXri (i64 G0), tglobaltlsaddr:$in)>; 527def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)), 528 (ADDXri (SETHIXi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>; 529def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)), 530 (XORXri (SETHIXi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>; 531 532// Blockaddress 533def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>; 534def : Pat<(SPlo tblockaddress:$in), (ORXri (i64 G0), tblockaddress:$in)>; 535 536// Add reg, lo. This is used when taking the addr of a global/constpool entry. 537def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDXri $r, tglobaladdr:$in)>; 538def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDXri $r, tconstpool:$in)>; 539def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)), 540 (ADDXri $r, tblockaddress:$in)>; 541} 542