• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1//===-- X86Schedule.td - X86 Scheduling Definitions --------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10// InstrSchedModel annotations for out-of-order CPUs.
11//
12// These annotations are independent of the itinerary classes defined below.
13
14// Instructions with folded loads need to read the memory operand immediately,
15// but other register operands don't have to be read until the load is ready.
16// These operands are marked with ReadAfterLd.
17def ReadAfterLd : SchedRead;
18
19// Instructions with both a load and a store folded are modeled as a folded
20// load + WriteRMW.
21def WriteRMW : SchedWrite;
22
23// Most instructions can fold loads, so almost every SchedWrite comes in two
24// variants: With and without a folded load.
25// An X86FoldableSchedWrite holds a reference to the corresponding SchedWrite
26// with a folded load.
27class X86FoldableSchedWrite : SchedWrite {
28  // The SchedWrite to use when a load is folded into the instruction.
29  SchedWrite Folded;
30}
31
32// Multiclass that produces a linked pair of SchedWrites.
33multiclass X86SchedWritePair {
34  // Register-Memory operation.
35  def Ld : SchedWrite;
36  // Register-Register operation.
37  def NAME : X86FoldableSchedWrite {
38    let Folded = !cast<SchedWrite>(NAME#"Ld");
39  }
40}
41
42// Arithmetic.
43defm WriteALU  : X86SchedWritePair; // Simple integer ALU op.
44defm WriteIMul : X86SchedWritePair; // Integer multiplication.
45def  WriteIMulH : SchedWrite;       // Integer multiplication, high part.
46defm WriteIDiv : X86SchedWritePair; // Integer division.
47def  WriteLEA  : SchedWrite;        // LEA instructions can't fold loads.
48
49// Integer shifts and rotates.
50defm WriteShift : X86SchedWritePair;
51
52// Loads, stores, and moves, not folded with other operations.
53def WriteLoad  : SchedWrite;
54def WriteStore : SchedWrite;
55def WriteMove  : SchedWrite;
56
57// Idioms that clear a register, like xorps %xmm0, %xmm0.
58// These can often bypass execution ports completely.
59def WriteZero : SchedWrite;
60
61// Branches don't produce values, so they have no latency, but they still
62// consume resources. Indirect branches can fold loads.
63defm WriteJump : X86SchedWritePair;
64
65// Floating point. This covers both scalar and vector operations.
66defm WriteFAdd   : X86SchedWritePair; // Floating point add/sub/compare.
67defm WriteFMul   : X86SchedWritePair; // Floating point multiplication.
68defm WriteFDiv   : X86SchedWritePair; // Floating point division.
69defm WriteFSqrt  : X86SchedWritePair; // Floating point square root.
70defm WriteFRcp   : X86SchedWritePair; // Floating point reciprocal estimate.
71defm WriteFRsqrt : X86SchedWritePair; // Floating point reciprocal square root estimate.
72defm WriteFMA    : X86SchedWritePair; // Fused Multiply Add.
73defm WriteFShuffle  : X86SchedWritePair; // Floating point vector shuffles.
74defm WriteFBlend  : X86SchedWritePair; // Floating point vector blends.
75defm WriteFVarBlend  : X86SchedWritePair; // Fp vector variable blends.
76
77// FMA Scheduling helper class.
78class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
79
80// Vector integer operations.
81defm WriteVecALU   : X86SchedWritePair; // Vector integer ALU op, no logicals.
82defm WriteVecShift : X86SchedWritePair; // Vector integer shifts.
83defm WriteVecIMul  : X86SchedWritePair; // Vector integer multiply.
84defm WriteShuffle  : X86SchedWritePair; // Vector shuffles.
85defm WriteBlend  : X86SchedWritePair; // Vector blends.
86defm WriteVarBlend  : X86SchedWritePair; // Vector variable blends.
87defm WriteMPSAD : X86SchedWritePair; // Vector MPSAD.
88
89// Vector bitwise operations.
90// These are often used on both floating point and integer vectors.
91defm WriteVecLogic : X86SchedWritePair; // Vector and/or/xor.
92
93// Conversion between integer and float.
94defm WriteCvtF2I : X86SchedWritePair; // Float -> Integer.
95defm WriteCvtI2F : X86SchedWritePair; // Integer -> Float.
96defm WriteCvtF2F : X86SchedWritePair; // Float -> Float size conversion.
97
98// Strings instructions.
99// Packed Compare Implicit Length Strings, Return Mask
100defm WritePCmpIStrM : X86SchedWritePair;
101// Packed Compare Explicit Length Strings, Return Mask
102defm WritePCmpEStrM : X86SchedWritePair;
103// Packed Compare Implicit Length Strings, Return Index
104defm WritePCmpIStrI : X86SchedWritePair;
105// Packed Compare Explicit Length Strings, Return Index
106defm WritePCmpEStrI : X86SchedWritePair;
107
108// AES instructions.
109defm WriteAESDecEnc : X86SchedWritePair; // Decryption, encryption.
110defm WriteAESIMC : X86SchedWritePair; // InvMixColumn.
111defm WriteAESKeyGen : X86SchedWritePair; // Key Generation.
112
113// Carry-less multiplication instructions.
114defm WriteCLMul : X86SchedWritePair;
115
116// Catch-all for expensive system instructions.
117def WriteSystem : SchedWrite;
118
119// AVX2.
120defm WriteFShuffle256 : X86SchedWritePair; // Fp 256-bit width vector shuffles.
121defm WriteShuffle256 : X86SchedWritePair; // 256-bit width vector shuffles.
122defm WriteVarVecShift : X86SchedWritePair; // Variable vector shifts.
123
124// Old microcoded instructions that nobody use.
125def WriteMicrocoded : SchedWrite;
126
127// Fence instructions.
128def WriteFence : SchedWrite;
129
130// Nop, not very useful expect it provides a model for nops!
131def WriteNop : SchedWrite;
132
133//===----------------------------------------------------------------------===//
134// Instruction Itinerary classes used for X86
135def IIC_ALU_MEM     : InstrItinClass;
136def IIC_ALU_NONMEM  : InstrItinClass;
137def IIC_LEA         : InstrItinClass;
138def IIC_LEA_16      : InstrItinClass;
139def IIC_MUL8        : InstrItinClass;
140def IIC_MUL16_MEM   : InstrItinClass;
141def IIC_MUL16_REG   : InstrItinClass;
142def IIC_MUL32_MEM   : InstrItinClass;
143def IIC_MUL32_REG   : InstrItinClass;
144def IIC_MUL64       : InstrItinClass;
145// imul by al, ax, eax, tax
146def IIC_IMUL8       : InstrItinClass;
147def IIC_IMUL16_MEM  : InstrItinClass;
148def IIC_IMUL16_REG  : InstrItinClass;
149def IIC_IMUL32_MEM  : InstrItinClass;
150def IIC_IMUL32_REG  : InstrItinClass;
151def IIC_IMUL64      : InstrItinClass;
152// imul reg by reg|mem
153def IIC_IMUL16_RM   : InstrItinClass;
154def IIC_IMUL16_RR   : InstrItinClass;
155def IIC_IMUL32_RM   : InstrItinClass;
156def IIC_IMUL32_RR   : InstrItinClass;
157def IIC_IMUL64_RM   : InstrItinClass;
158def IIC_IMUL64_RR   : InstrItinClass;
159// imul reg = reg/mem * imm
160def IIC_IMUL16_RMI  : InstrItinClass;
161def IIC_IMUL16_RRI  : InstrItinClass;
162def IIC_IMUL32_RMI  : InstrItinClass;
163def IIC_IMUL32_RRI  : InstrItinClass;
164def IIC_IMUL64_RMI  : InstrItinClass;
165def IIC_IMUL64_RRI  : InstrItinClass;
166// div
167def IIC_DIV8_MEM    : InstrItinClass;
168def IIC_DIV8_REG    : InstrItinClass;
169def IIC_DIV16       : InstrItinClass;
170def IIC_DIV32       : InstrItinClass;
171def IIC_DIV64       : InstrItinClass;
172// idiv
173def IIC_IDIV8       : InstrItinClass;
174def IIC_IDIV16      : InstrItinClass;
175def IIC_IDIV32      : InstrItinClass;
176def IIC_IDIV64      : InstrItinClass;
177// neg/not/inc/dec
178def IIC_UNARY_REG   : InstrItinClass;
179def IIC_UNARY_MEM   : InstrItinClass;
180// add/sub/and/or/xor/sbc/cmp/test
181def IIC_BIN_MEM     : InstrItinClass;
182def IIC_BIN_NONMEM  : InstrItinClass;
183// adc/sbc
184def IIC_BIN_CARRY_MEM     : InstrItinClass;
185def IIC_BIN_CARRY_NONMEM  : InstrItinClass;
186// shift/rotate
187def IIC_SR          : InstrItinClass;
188// shift double
189def IIC_SHD16_REG_IM : InstrItinClass;
190def IIC_SHD16_REG_CL : InstrItinClass;
191def IIC_SHD16_MEM_IM : InstrItinClass;
192def IIC_SHD16_MEM_CL : InstrItinClass;
193def IIC_SHD32_REG_IM : InstrItinClass;
194def IIC_SHD32_REG_CL : InstrItinClass;
195def IIC_SHD32_MEM_IM : InstrItinClass;
196def IIC_SHD32_MEM_CL : InstrItinClass;
197def IIC_SHD64_REG_IM : InstrItinClass;
198def IIC_SHD64_REG_CL : InstrItinClass;
199def IIC_SHD64_MEM_IM : InstrItinClass;
200def IIC_SHD64_MEM_CL : InstrItinClass;
201// cmov
202def IIC_CMOV16_RM : InstrItinClass;
203def IIC_CMOV16_RR : InstrItinClass;
204def IIC_CMOV32_RM : InstrItinClass;
205def IIC_CMOV32_RR : InstrItinClass;
206def IIC_CMOV64_RM : InstrItinClass;
207def IIC_CMOV64_RR : InstrItinClass;
208// set
209def IIC_SET_R : InstrItinClass;
210def IIC_SET_M : InstrItinClass;
211// jmp/jcc/jcxz
212def IIC_Jcc : InstrItinClass;
213def IIC_JCXZ : InstrItinClass;
214def IIC_JMP_REL : InstrItinClass;
215def IIC_JMP_REG : InstrItinClass;
216def IIC_JMP_MEM : InstrItinClass;
217def IIC_JMP_FAR_MEM : InstrItinClass;
218def IIC_JMP_FAR_PTR : InstrItinClass;
219// loop
220def IIC_LOOP : InstrItinClass;
221def IIC_LOOPE : InstrItinClass;
222def IIC_LOOPNE : InstrItinClass;
223// call
224def IIC_CALL_RI : InstrItinClass;
225def IIC_CALL_MEM : InstrItinClass;
226def IIC_CALL_FAR_MEM : InstrItinClass;
227def IIC_CALL_FAR_PTR : InstrItinClass;
228// ret
229def IIC_RET : InstrItinClass;
230def IIC_RET_IMM : InstrItinClass;
231//sign extension movs
232def IIC_MOVSX : InstrItinClass;
233def IIC_MOVSX_R16_R8 : InstrItinClass;
234def IIC_MOVSX_R16_M8 : InstrItinClass;
235def IIC_MOVSX_R16_R16 : InstrItinClass;
236def IIC_MOVSX_R32_R32 : InstrItinClass;
237//zero extension movs
238def IIC_MOVZX : InstrItinClass;
239def IIC_MOVZX_R16_R8 : InstrItinClass;
240def IIC_MOVZX_R16_M8 : InstrItinClass;
241
242def IIC_REP_MOVS : InstrItinClass;
243def IIC_REP_STOS : InstrItinClass;
244
245// SSE scalar/parallel binary operations
246def IIC_SSE_ALU_F32S_RR : InstrItinClass;
247def IIC_SSE_ALU_F32S_RM : InstrItinClass;
248def IIC_SSE_ALU_F64S_RR : InstrItinClass;
249def IIC_SSE_ALU_F64S_RM : InstrItinClass;
250def IIC_SSE_MUL_F32S_RR : InstrItinClass;
251def IIC_SSE_MUL_F32S_RM : InstrItinClass;
252def IIC_SSE_MUL_F64S_RR : InstrItinClass;
253def IIC_SSE_MUL_F64S_RM : InstrItinClass;
254def IIC_SSE_DIV_F32S_RR : InstrItinClass;
255def IIC_SSE_DIV_F32S_RM : InstrItinClass;
256def IIC_SSE_DIV_F64S_RR : InstrItinClass;
257def IIC_SSE_DIV_F64S_RM : InstrItinClass;
258def IIC_SSE_ALU_F32P_RR : InstrItinClass;
259def IIC_SSE_ALU_F32P_RM : InstrItinClass;
260def IIC_SSE_ALU_F64P_RR : InstrItinClass;
261def IIC_SSE_ALU_F64P_RM : InstrItinClass;
262def IIC_SSE_MUL_F32P_RR : InstrItinClass;
263def IIC_SSE_MUL_F32P_RM : InstrItinClass;
264def IIC_SSE_MUL_F64P_RR : InstrItinClass;
265def IIC_SSE_MUL_F64P_RM : InstrItinClass;
266def IIC_SSE_DIV_F32P_RR : InstrItinClass;
267def IIC_SSE_DIV_F32P_RM : InstrItinClass;
268def IIC_SSE_DIV_F64P_RR : InstrItinClass;
269def IIC_SSE_DIV_F64P_RM : InstrItinClass;
270
271def IIC_SSE_COMIS_RR : InstrItinClass;
272def IIC_SSE_COMIS_RM : InstrItinClass;
273
274def IIC_SSE_HADDSUB_RR : InstrItinClass;
275def IIC_SSE_HADDSUB_RM : InstrItinClass;
276
277def IIC_SSE_BIT_P_RR  : InstrItinClass;
278def IIC_SSE_BIT_P_RM  : InstrItinClass;
279
280def IIC_SSE_INTALU_P_RR  : InstrItinClass;
281def IIC_SSE_INTALU_P_RM  : InstrItinClass;
282def IIC_SSE_INTALUQ_P_RR  : InstrItinClass;
283def IIC_SSE_INTALUQ_P_RM  : InstrItinClass;
284
285def IIC_SSE_INTMUL_P_RR : InstrItinClass;
286def IIC_SSE_INTMUL_P_RM : InstrItinClass;
287
288def IIC_SSE_INTSH_P_RR : InstrItinClass;
289def IIC_SSE_INTSH_P_RM : InstrItinClass;
290def IIC_SSE_INTSH_P_RI : InstrItinClass;
291
292def IIC_SSE_INTSHDQ_P_RI : InstrItinClass;
293
294def IIC_SSE_SHUFP : InstrItinClass;
295def IIC_SSE_PSHUF_RI : InstrItinClass;
296def IIC_SSE_PSHUF_MI : InstrItinClass;
297
298def IIC_SSE_UNPCK : InstrItinClass;
299
300def IIC_SSE_MOVMSK : InstrItinClass;
301def IIC_SSE_MASKMOV : InstrItinClass;
302
303def IIC_SSE_PEXTRW : InstrItinClass;
304def IIC_SSE_PINSRW : InstrItinClass;
305
306def IIC_SSE_PABS_RR : InstrItinClass;
307def IIC_SSE_PABS_RM : InstrItinClass;
308
309def IIC_SSE_SQRTPS_RR : InstrItinClass;
310def IIC_SSE_SQRTPS_RM : InstrItinClass;
311def IIC_SSE_SQRTSS_RR : InstrItinClass;
312def IIC_SSE_SQRTSS_RM : InstrItinClass;
313def IIC_SSE_SQRTPD_RR : InstrItinClass;
314def IIC_SSE_SQRTPD_RM : InstrItinClass;
315def IIC_SSE_SQRTSD_RR : InstrItinClass;
316def IIC_SSE_SQRTSD_RM : InstrItinClass;
317
318def IIC_SSE_RSQRTPS_RR : InstrItinClass;
319def IIC_SSE_RSQRTPS_RM : InstrItinClass;
320def IIC_SSE_RSQRTSS_RR : InstrItinClass;
321def IIC_SSE_RSQRTSS_RM : InstrItinClass;
322
323def IIC_SSE_RCPP_RR : InstrItinClass;
324def IIC_SSE_RCPP_RM : InstrItinClass;
325def IIC_SSE_RCPS_RR : InstrItinClass;
326def IIC_SSE_RCPS_RM : InstrItinClass;
327
328def IIC_SSE_MOV_S_RR : InstrItinClass;
329def IIC_SSE_MOV_S_RM : InstrItinClass;
330def IIC_SSE_MOV_S_MR : InstrItinClass;
331
332def IIC_SSE_MOVA_P_RR : InstrItinClass;
333def IIC_SSE_MOVA_P_RM : InstrItinClass;
334def IIC_SSE_MOVA_P_MR : InstrItinClass;
335
336def IIC_SSE_MOVU_P_RR : InstrItinClass;
337def IIC_SSE_MOVU_P_RM : InstrItinClass;
338def IIC_SSE_MOVU_P_MR : InstrItinClass;
339
340def IIC_SSE_MOVDQ : InstrItinClass;
341def IIC_SSE_MOVD_ToGP : InstrItinClass;
342def IIC_SSE_MOVQ_RR : InstrItinClass;
343
344def IIC_SSE_MOV_LH : InstrItinClass;
345
346def IIC_SSE_LDDQU : InstrItinClass;
347
348def IIC_SSE_MOVNT : InstrItinClass;
349
350def IIC_SSE_PHADDSUBD_RR : InstrItinClass;
351def IIC_SSE_PHADDSUBD_RM : InstrItinClass;
352def IIC_SSE_PHADDSUBSW_RR : InstrItinClass;
353def IIC_SSE_PHADDSUBSW_RM : InstrItinClass;
354def IIC_SSE_PHADDSUBW_RR : InstrItinClass;
355def IIC_SSE_PHADDSUBW_RM : InstrItinClass;
356def IIC_SSE_PSHUFB_RR : InstrItinClass;
357def IIC_SSE_PSHUFB_RM : InstrItinClass;
358def IIC_SSE_PSIGN_RR : InstrItinClass;
359def IIC_SSE_PSIGN_RM : InstrItinClass;
360
361def IIC_SSE_PMADD : InstrItinClass;
362def IIC_SSE_PMULHRSW : InstrItinClass;
363def IIC_SSE_PALIGNRR : InstrItinClass;
364def IIC_SSE_PALIGNRM : InstrItinClass;
365def IIC_SSE_MWAIT : InstrItinClass;
366def IIC_SSE_MONITOR : InstrItinClass;
367def IIC_SSE_MWAITX : InstrItinClass;
368def IIC_SSE_MONITORX : InstrItinClass;
369
370def IIC_SSE_PREFETCH : InstrItinClass;
371def IIC_SSE_PAUSE : InstrItinClass;
372def IIC_SSE_LFENCE : InstrItinClass;
373def IIC_SSE_MFENCE : InstrItinClass;
374def IIC_SSE_SFENCE : InstrItinClass;
375def IIC_SSE_LDMXCSR : InstrItinClass;
376def IIC_SSE_STMXCSR : InstrItinClass;
377
378def IIC_SSE_CVT_PD_RR : InstrItinClass;
379def IIC_SSE_CVT_PD_RM : InstrItinClass;
380def IIC_SSE_CVT_PS_RR : InstrItinClass;
381def IIC_SSE_CVT_PS_RM : InstrItinClass;
382def IIC_SSE_CVT_PI2PS_RR : InstrItinClass;
383def IIC_SSE_CVT_PI2PS_RM : InstrItinClass;
384def IIC_SSE_CVT_Scalar_RR : InstrItinClass;
385def IIC_SSE_CVT_Scalar_RM : InstrItinClass;
386def IIC_SSE_CVT_SS2SI32_RM : InstrItinClass;
387def IIC_SSE_CVT_SS2SI32_RR : InstrItinClass;
388def IIC_SSE_CVT_SS2SI64_RM : InstrItinClass;
389def IIC_SSE_CVT_SS2SI64_RR : InstrItinClass;
390def IIC_SSE_CVT_SD2SI_RM : InstrItinClass;
391def IIC_SSE_CVT_SD2SI_RR : InstrItinClass;
392
393// MMX
394def IIC_MMX_MOV_MM_RM : InstrItinClass;
395def IIC_MMX_MOV_REG_MM : InstrItinClass;
396def IIC_MMX_MOVQ_RM : InstrItinClass;
397def IIC_MMX_MOVQ_RR : InstrItinClass;
398
399def IIC_MMX_ALU_RM : InstrItinClass;
400def IIC_MMX_ALU_RR : InstrItinClass;
401def IIC_MMX_ALUQ_RM : InstrItinClass;
402def IIC_MMX_ALUQ_RR : InstrItinClass;
403def IIC_MMX_PHADDSUBW_RM : InstrItinClass;
404def IIC_MMX_PHADDSUBW_RR : InstrItinClass;
405def IIC_MMX_PHADDSUBD_RM : InstrItinClass;
406def IIC_MMX_PHADDSUBD_RR : InstrItinClass;
407def IIC_MMX_PMUL : InstrItinClass;
408def IIC_MMX_MISC_FUNC_MEM : InstrItinClass;
409def IIC_MMX_MISC_FUNC_REG : InstrItinClass;
410def IIC_MMX_PSADBW : InstrItinClass;
411def IIC_MMX_SHIFT_RI : InstrItinClass;
412def IIC_MMX_SHIFT_RM : InstrItinClass;
413def IIC_MMX_SHIFT_RR : InstrItinClass;
414def IIC_MMX_UNPCK_H_RM : InstrItinClass;
415def IIC_MMX_UNPCK_H_RR : InstrItinClass;
416def IIC_MMX_UNPCK_L : InstrItinClass;
417def IIC_MMX_PCK_RM : InstrItinClass;
418def IIC_MMX_PCK_RR : InstrItinClass;
419def IIC_MMX_PSHUF : InstrItinClass;
420def IIC_MMX_PEXTR : InstrItinClass;
421def IIC_MMX_PINSRW : InstrItinClass;
422def IIC_MMX_MASKMOV : InstrItinClass;
423
424def IIC_MMX_CVT_PD_RR : InstrItinClass;
425def IIC_MMX_CVT_PD_RM : InstrItinClass;
426def IIC_MMX_CVT_PS_RR : InstrItinClass;
427def IIC_MMX_CVT_PS_RM : InstrItinClass;
428
429def IIC_CMPX_LOCK : InstrItinClass;
430def IIC_CMPX_LOCK_8 : InstrItinClass;
431def IIC_CMPX_LOCK_8B : InstrItinClass;
432def IIC_CMPX_LOCK_16B : InstrItinClass;
433
434def IIC_XADD_LOCK_MEM : InstrItinClass;
435def IIC_XADD_LOCK_MEM8 : InstrItinClass;
436
437def IIC_FILD : InstrItinClass;
438def IIC_FLD : InstrItinClass;
439def IIC_FLD80 : InstrItinClass;
440def IIC_FST : InstrItinClass;
441def IIC_FST80 : InstrItinClass;
442def IIC_FIST : InstrItinClass;
443def IIC_FLDZ : InstrItinClass;
444def IIC_FUCOM : InstrItinClass;
445def IIC_FUCOMI : InstrItinClass;
446def IIC_FCOMI : InstrItinClass;
447def IIC_FNSTSW : InstrItinClass;
448def IIC_FNSTCW : InstrItinClass;
449def IIC_FLDCW : InstrItinClass;
450def IIC_FNINIT : InstrItinClass;
451def IIC_FFREE : InstrItinClass;
452def IIC_FNCLEX : InstrItinClass;
453def IIC_WAIT : InstrItinClass;
454def IIC_FXAM : InstrItinClass;
455def IIC_FNOP : InstrItinClass;
456def IIC_FLDL : InstrItinClass;
457def IIC_F2XM1 : InstrItinClass;
458def IIC_FYL2X : InstrItinClass;
459def IIC_FPTAN : InstrItinClass;
460def IIC_FPATAN : InstrItinClass;
461def IIC_FXTRACT : InstrItinClass;
462def IIC_FPREM1 : InstrItinClass;
463def IIC_FPSTP : InstrItinClass;
464def IIC_FPREM : InstrItinClass;
465def IIC_FYL2XP1 : InstrItinClass;
466def IIC_FSINCOS : InstrItinClass;
467def IIC_FRNDINT : InstrItinClass;
468def IIC_FSCALE : InstrItinClass;
469def IIC_FCOMPP : InstrItinClass;
470def IIC_FXSAVE : InstrItinClass;
471def IIC_FXRSTOR : InstrItinClass;
472
473def IIC_FXCH : InstrItinClass;
474
475// System instructions
476def IIC_CPUID : InstrItinClass;
477def IIC_INT : InstrItinClass;
478def IIC_INT3 : InstrItinClass;
479def IIC_INVD : InstrItinClass;
480def IIC_INVLPG : InstrItinClass;
481def IIC_IRET : InstrItinClass;
482def IIC_HLT : InstrItinClass;
483def IIC_LXS : InstrItinClass;
484def IIC_LTR : InstrItinClass;
485def IIC_RDTSC : InstrItinClass;
486def IIC_RSM : InstrItinClass;
487def IIC_SIDT : InstrItinClass;
488def IIC_SGDT : InstrItinClass;
489def IIC_SLDT : InstrItinClass;
490def IIC_STR : InstrItinClass;
491def IIC_SWAPGS : InstrItinClass;
492def IIC_SYSCALL : InstrItinClass;
493def IIC_SYS_ENTER_EXIT : InstrItinClass;
494def IIC_IN_RR : InstrItinClass;
495def IIC_IN_RI : InstrItinClass;
496def IIC_OUT_RR : InstrItinClass;
497def IIC_OUT_IR : InstrItinClass;
498def IIC_INS : InstrItinClass;
499def IIC_MOV_REG_DR : InstrItinClass;
500def IIC_MOV_DR_REG : InstrItinClass;
501def IIC_MOV_REG_CR : InstrItinClass;
502def IIC_MOV_CR_REG : InstrItinClass;
503def IIC_MOV_REG_SR : InstrItinClass;
504def IIC_MOV_MEM_SR : InstrItinClass;
505def IIC_MOV_SR_REG : InstrItinClass;
506def IIC_MOV_SR_MEM : InstrItinClass;
507def IIC_LAR_RM : InstrItinClass;
508def IIC_LAR_RR : InstrItinClass;
509def IIC_LSL_RM : InstrItinClass;
510def IIC_LSL_RR : InstrItinClass;
511def IIC_LGDT : InstrItinClass;
512def IIC_LIDT : InstrItinClass;
513def IIC_LLDT_REG : InstrItinClass;
514def IIC_LLDT_MEM : InstrItinClass;
515def IIC_PUSH_CS : InstrItinClass;
516def IIC_PUSH_SR : InstrItinClass;
517def IIC_POP_SR : InstrItinClass;
518def IIC_POP_SR_SS : InstrItinClass;
519def IIC_VERR : InstrItinClass;
520def IIC_VERW_REG : InstrItinClass;
521def IIC_VERW_MEM : InstrItinClass;
522def IIC_WRMSR : InstrItinClass;
523def IIC_RDMSR : InstrItinClass;
524def IIC_RDPMC : InstrItinClass;
525def IIC_SMSW : InstrItinClass;
526def IIC_LMSW_REG : InstrItinClass;
527def IIC_LMSW_MEM : InstrItinClass;
528def IIC_ENTER : InstrItinClass;
529def IIC_LEAVE : InstrItinClass;
530def IIC_POP_MEM : InstrItinClass;
531def IIC_POP_REG16 : InstrItinClass;
532def IIC_POP_REG : InstrItinClass;
533def IIC_POP_F : InstrItinClass;
534def IIC_POP_FD : InstrItinClass;
535def IIC_POP_A : InstrItinClass;
536def IIC_PUSH_IMM : InstrItinClass;
537def IIC_PUSH_MEM : InstrItinClass;
538def IIC_PUSH_REG : InstrItinClass;
539def IIC_PUSH_F : InstrItinClass;
540def IIC_PUSH_A : InstrItinClass;
541def IIC_BSWAP : InstrItinClass;
542def IIC_BIT_SCAN_MEM : InstrItinClass;
543def IIC_BIT_SCAN_REG : InstrItinClass;
544def IIC_MOVS : InstrItinClass;
545def IIC_STOS : InstrItinClass;
546def IIC_SCAS : InstrItinClass;
547def IIC_CMPS : InstrItinClass;
548def IIC_MOV : InstrItinClass;
549def IIC_MOV_MEM : InstrItinClass;
550def IIC_AHF : InstrItinClass;
551def IIC_BT_MI : InstrItinClass;
552def IIC_BT_MR : InstrItinClass;
553def IIC_BT_RI : InstrItinClass;
554def IIC_BT_RR : InstrItinClass;
555def IIC_BTX_MI : InstrItinClass;
556def IIC_BTX_MR : InstrItinClass;
557def IIC_BTX_RI : InstrItinClass;
558def IIC_BTX_RR : InstrItinClass;
559def IIC_XCHG_REG : InstrItinClass;
560def IIC_XCHG_MEM : InstrItinClass;
561def IIC_XADD_REG : InstrItinClass;
562def IIC_XADD_MEM : InstrItinClass;
563def IIC_CMPXCHG_MEM : InstrItinClass;
564def IIC_CMPXCHG_REG : InstrItinClass;
565def IIC_CMPXCHG_MEM8 : InstrItinClass;
566def IIC_CMPXCHG_REG8 : InstrItinClass;
567def IIC_CMPXCHG_8B : InstrItinClass;
568def IIC_CMPXCHG_16B : InstrItinClass;
569def IIC_LODS : InstrItinClass;
570def IIC_OUTS : InstrItinClass;
571def IIC_CLC : InstrItinClass;
572def IIC_CLD : InstrItinClass;
573def IIC_CLI : InstrItinClass;
574def IIC_CMC : InstrItinClass;
575def IIC_CLTS : InstrItinClass;
576def IIC_STC : InstrItinClass;
577def IIC_STI : InstrItinClass;
578def IIC_STD : InstrItinClass;
579def IIC_XLAT : InstrItinClass;
580def IIC_AAA : InstrItinClass;
581def IIC_AAD : InstrItinClass;
582def IIC_AAM : InstrItinClass;
583def IIC_AAS : InstrItinClass;
584def IIC_DAA : InstrItinClass;
585def IIC_DAS : InstrItinClass;
586def IIC_BOUND : InstrItinClass;
587def IIC_ARPL_REG : InstrItinClass;
588def IIC_ARPL_MEM : InstrItinClass;
589def IIC_MOVBE : InstrItinClass;
590def IIC_AES   : InstrItinClass;
591def IIC_BLEND_MEM : InstrItinClass;
592def IIC_BLEND_NOMEM : InstrItinClass;
593def IIC_CBW   : InstrItinClass;
594def IIC_CRC32_REG : InstrItinClass;
595def IIC_CRC32_MEM : InstrItinClass;
596def IIC_SSE_DPPD_RR : InstrItinClass;
597def IIC_SSE_DPPD_RM : InstrItinClass;
598def IIC_SSE_DPPS_RR : InstrItinClass;
599def IIC_SSE_DPPS_RM : InstrItinClass;
600def IIC_MMX_EMMS : InstrItinClass;
601def IIC_SSE_EXTRACTPS_RR : InstrItinClass;
602def IIC_SSE_EXTRACTPS_RM : InstrItinClass;
603def IIC_SSE_INSERTPS_RR : InstrItinClass;
604def IIC_SSE_INSERTPS_RM : InstrItinClass;
605def IIC_SSE_MPSADBW_RR : InstrItinClass;
606def IIC_SSE_MPSADBW_RM : InstrItinClass;
607def IIC_SSE_PMULLD_RR : InstrItinClass;
608def IIC_SSE_PMULLD_RM : InstrItinClass;
609def IIC_SSE_ROUNDPS_REG : InstrItinClass;
610def IIC_SSE_ROUNDPS_MEM : InstrItinClass;
611def IIC_SSE_ROUNDPD_REG : InstrItinClass;
612def IIC_SSE_ROUNDPD_MEM : InstrItinClass;
613def IIC_SSE_POPCNT_RR : InstrItinClass;
614def IIC_SSE_POPCNT_RM : InstrItinClass;
615def IIC_SSE_PCLMULQDQ_RR : InstrItinClass;
616def IIC_SSE_PCLMULQDQ_RM : InstrItinClass;
617
618def IIC_NOP : InstrItinClass;
619
620//===----------------------------------------------------------------------===//
621// Processor instruction itineraries.
622
623// IssueWidth is analogous to the number of decode units. Core and its
624// descendents, including Nehalem and SandyBridge have 4 decoders.
625// Resources beyond the decoder operate on micro-ops and are bufferred
626// so adjacent micro-ops don't directly compete.
627//
628// MicroOpBufferSize > 1 indicates that RAW dependencies can be
629// decoded in the same cycle. The value 32 is a reasonably arbitrary
630// number of in-flight instructions.
631//
632// HighLatency=10 is optimistic. X86InstrInfo::isHighLatencyDef
633// indicates high latency opcodes. Alternatively, InstrItinData
634// entries may be included here to define specific operand
635// latencies. Since these latencies are not used for pipeline hazards,
636// they do not need to be exact.
637//
638// The GenericX86Model contains no instruction itineraries
639// and disables PostRAScheduler.
640class GenericX86Model : SchedMachineModel {
641  let IssueWidth = 4;
642  let MicroOpBufferSize = 32;
643  let LoadLatency = 4;
644  let HighLatency = 10;
645  let PostRAScheduler = 0;
646  let CompleteModel = 0;
647}
648
649def GenericModel : GenericX86Model;
650
651// Define a model with the PostRAScheduler enabled.
652def GenericPostRAModel : GenericX86Model {
653  let PostRAScheduler = 1;
654}
655
656include "X86ScheduleAtom.td"
657include "X86SchedSandyBridge.td"
658include "X86SchedHaswell.td"
659include "X86ScheduleSLM.td"
660include "X86ScheduleBtVer2.td"
661
662