1; RUN: llc %s -o - -verify-machineinstrs -mtriple=arm64-none-linux-gnu | FileCheck %s 2 3; This is the analogue of AArch64's file of the same name. It's mostly testing 4; some form of correct lowering occurs, the tests are a little artificial but I 5; strongly suspect there's room for improved CodeGen (FIXME). 6 7define i64 @test_sext_extr_cmp_0(<1 x i64> %v1, <1 x i64> %v2) { 8; CHECK-LABEL: test_sext_extr_cmp_0: 9; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}} 10; CHECK: cset 11 %1 = icmp sge <1 x i64> %v1, %v2 12 %2 = extractelement <1 x i1> %1, i32 0 13 %vget_lane = sext i1 %2 to i64 14 ret i64 %vget_lane 15} 16 17define i64 @test_sext_extr_cmp_1(<1 x double> %v1, <1 x double> %v2) { 18; CHECK-LABEL: test_sext_extr_cmp_1: 19; CHECK: fcmp {{d[0-9]+}}, {{d[0-9]+}} 20 %1 = fcmp oeq <1 x double> %v1, %v2 21 %2 = extractelement <1 x i1> %1, i32 0 22 %vget_lane = sext i1 %2 to i64 23 ret i64 %vget_lane 24} 25 26define <1 x i64> @test_select_v1i1_0(<1 x i64> %v1, <1 x i64> %v2, <1 x i64> %v3) { 27; CHECK-LABEL: test_select_v1i1_0: 28; CHECK: cmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}} 29; CHECK: bic v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b 30 %1 = icmp eq <1 x i64> %v1, %v2 31 %res = select <1 x i1> %1, <1 x i64> zeroinitializer, <1 x i64> %v3 32 ret <1 x i64> %res 33} 34 35define <1 x i64> @test_select_v1i1_1(<1 x double> %v1, <1 x double> %v2, <1 x i64> %v3) { 36; CHECK-LABEL: test_select_v1i1_1: 37; CHECK: fcmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}} 38; CHECK: bic v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b 39 %1 = fcmp oeq <1 x double> %v1, %v2 40 %res = select <1 x i1> %1, <1 x i64> zeroinitializer, <1 x i64> %v3 41 ret <1 x i64> %res 42} 43 44define <1 x double> @test_select_v1i1_2(<1 x i64> %v1, <1 x i64> %v2, <1 x double> %v3) { 45; CHECK-LABEL: test_select_v1i1_2: 46; CHECK: cmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}} 47; CHECK: bic v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b 48 %1 = icmp eq <1 x i64> %v1, %v2 49 %res = select <1 x i1> %1, <1 x double> zeroinitializer, <1 x double> %v3 50 ret <1 x double> %res 51} 52 53; For v1i64, it's not clear which of the vector or scalar compare is better. 54; Let's stick to the vector form, like for all other vector selects fed by a 55; scalar setcc. If anything, it exposes more ILP. 56define <1 x i64> @test_select_v1i1_3(i64 %lhs, i64 %rhs, <1 x i64> %v3) { 57; CHECK-LABEL: test_select_v1i1_3: 58; CHECK: fmov d{{[0-9]+}}, x{{[0-9]+}} 59; CHECK: fmov d{{[0-9]+}}, x{{[0-9]+}} 60; CHECK: cmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}} 61; CHECK: bic v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b 62 %tst = icmp eq i64 %lhs, %rhs 63 %evil = insertelement <1 x i1> undef, i1 %tst, i32 0 64 %res = select <1 x i1> %evil, <1 x i64> zeroinitializer, <1 x i64> %v3 65 ret <1 x i64> %res 66} 67 68define i32 @test_br_extr_cmp(<1 x i64> %v1, <1 x i64> %v2) { 69; CHECK-LABEL: test_br_extr_cmp: 70; CHECK: cmp x{{[0-9]+}}, x{{[0-9]+}} 71 %1 = icmp eq <1 x i64> %v1, %v2 72 %2 = extractelement <1 x i1> %1, i32 0 73 br i1 %2, label %if.end, label %if.then 74 75if.then: 76 ret i32 0; 77 78if.end: 79 ret i32 1; 80} 81