1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s 2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s 3 4; CHECK-LABEL: {{^}}inline_asm: 5; CHECK: s_endpgm 6; CHECK: s_endpgm 7define void @inline_asm(i32 addrspace(1)* %out) { 8entry: 9 store i32 5, i32 addrspace(1)* %out 10 call void asm sideeffect "s_endpgm", ""() 11 ret void 12} 13 14; CHECK-LABEL: {{^}}inline_asm_shader: 15; CHECK: s_endpgm 16; CHECK: s_endpgm 17define amdgpu_ps void @inline_asm_shader() { 18entry: 19 call void asm sideeffect "s_endpgm", ""() 20 ret void 21} 22 23 24; CHECK: {{^}}branch_on_asm: 25; Make sure inline assembly is treted as divergent. 26; CHECK: s_mov_b32 s{{[0-9]+}}, 0 27; CHECK: s_and_saveexec_b64 28define void @branch_on_asm(i32 addrspace(1)* %out) { 29 %zero = call i32 asm "s_mov_b32 $0, 0", "=s"() 30 %cmp = icmp eq i32 %zero, 0 31 br i1 %cmp, label %if, label %endif 32 33if: 34 store i32 0, i32 addrspace(1)* %out 35 br label %endif 36 37endif: 38 ret void 39} 40 41; CHECK-LABEL: {{^}}v_cmp_asm: 42; CHECK: v_mov_b32_e32 [[SRC:v[0-9]+]], s{{[0-9]+}} 43; CHECK: v_cmp_ne_i32_e64 s{{\[}}[[MASK_LO:[0-9]+]]:[[MASK_HI:[0-9]+]]{{\]}}, 0, [[SRC]] 44; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[MASK_LO]] 45; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[MASK_HI]] 46; CHECK: buffer_store_dwordx2 v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} 47define void @v_cmp_asm(i64 addrspace(1)* %out, i32 %in) { 48 %sgpr = tail call i64 asm "v_cmp_ne_i32_e64 $0, 0, $1", "=s,v"(i32 %in) 49 store i64 %sgpr, i64 addrspace(1)* %out 50 ret void 51} 52 53; CHECK-LABEL: {{^}}code_size_inline_asm: 54; CHECK: codeLenInByte = 12 55define void @code_size_inline_asm(i32 addrspace(1)* %out) { 56entry: 57 call void asm sideeffect "v_nop_e64", ""() 58 ret void 59} 60 61; All inlineasm instructions are assumed to be the maximum size 62; CHECK-LABEL: {{^}}code_size_inline_asm_small_inst: 63; CHECK: codeLenInByte = 12 64define void @code_size_inline_asm_small_inst(i32 addrspace(1)* %out) { 65entry: 66 call void asm sideeffect "v_nop_e32", ""() 67 ret void 68} 69 70; CHECK-LABEL: {{^}}code_size_inline_asm_2_inst: 71; CHECK: codeLenInByte = 20 72define void @code_size_inline_asm_2_inst(i32 addrspace(1)* %out) { 73entry: 74 call void asm sideeffect " 75 v_nop_e64 76 v_nop_e64 77 ", ""() 78 ret void 79} 80 81; CHECK-LABEL: {{^}}code_size_inline_asm_2_inst_extra_newline: 82; CHECK: codeLenInByte = 20 83define void @code_size_inline_asm_2_inst_extra_newline(i32 addrspace(1)* %out) { 84entry: 85 call void asm sideeffect " 86 v_nop_e64 87 88 v_nop_e64 89 ", ""() 90 ret void 91} 92 93; CHECK-LABEL: {{^}}code_size_inline_asm_0_inst: 94; CHECK: codeLenInByte = 4 95define void @code_size_inline_asm_0_inst(i32 addrspace(1)* %out) { 96entry: 97 call void asm sideeffect "", ""() 98 ret void 99} 100 101; CHECK-LABEL: {{^}}code_size_inline_asm_1_comment: 102; CHECK: codeLenInByte = 4 103define void @code_size_inline_asm_1_comment(i32 addrspace(1)* %out) { 104entry: 105 call void asm sideeffect "; comment", ""() 106 ret void 107} 108 109; CHECK-LABEL: {{^}}code_size_inline_asm_newline_1_comment: 110; CHECK: codeLenInByte = 4 111define void @code_size_inline_asm_newline_1_comment(i32 addrspace(1)* %out) { 112entry: 113 call void asm sideeffect " 114; comment", ""() 115 ret void 116} 117 118; CHECK-LABEL: {{^}}code_size_inline_asm_1_comment_newline: 119; CHECK: codeLenInByte = 4 120define void @code_size_inline_asm_1_comment_newline(i32 addrspace(1)* %out) { 121entry: 122 call void asm sideeffect "; comment 123", ""() 124 ret void 125} 126 127; CHECK-LABEL: {{^}}code_size_inline_asm_2_comments_line: 128; CHECK: codeLenInByte = 4 129define void @code_size_inline_asm_2_comments_line(i32 addrspace(1)* %out) { 130entry: 131 call void asm sideeffect "; first comment ; second comment", ""() 132 ret void 133} 134 135; CHECK-LABEL: {{^}}code_size_inline_asm_2_comments_line_nospace: 136; CHECK: codeLenInByte = 4 137define void @code_size_inline_asm_2_comments_line_nospace(i32 addrspace(1)* %out) { 138entry: 139 call void asm sideeffect "; first comment;second comment", ""() 140 ret void 141} 142 143; CHECK-LABEL: {{^}}code_size_inline_asm_mixed_comments0: 144; CHECK: codeLenInByte = 20 145define void @code_size_inline_asm_mixed_comments0(i32 addrspace(1)* %out) { 146entry: 147 call void asm sideeffect "; comment 148 v_nop_e64 ; inline comment 149; separate comment 150 v_nop_e64 151 152 ; trailing comment 153 ; extra comment 154 ", ""() 155 ret void 156} 157 158; CHECK-LABEL: {{^}}code_size_inline_asm_mixed_comments1: 159; CHECK: codeLenInByte = 20 160define void @code_size_inline_asm_mixed_comments1(i32 addrspace(1)* %out) { 161entry: 162 call void asm sideeffect "v_nop_e64 ; inline comment 163; separate comment 164 v_nop_e64 165 166 ; trailing comment 167 ; extra comment 168 ", ""() 169 ret void 170} 171 172; CHECK-LABEL: {{^}}code_size_inline_asm_mixed_comments_operands: 173; CHECK: codeLenInByte = 20 174define void @code_size_inline_asm_mixed_comments_operands(i32 addrspace(1)* %out) { 175entry: 176 call void asm sideeffect "; comment 177 v_add_i32_e32 v0, vcc, v1, v2 ; inline comment 178; separate comment 179 v_bfrev_b32_e32 v0, 1 180 181 ; trailing comment 182 ; extra comment 183 ", ""() 184 ret void 185} 186