1;RUN: llc < %s -march=amdgcn -mcpu=verde | FileCheck %s 2;RUN: llc < %s -march=amdgcn -mcpu=tonga | FileCheck %s 3 4; CHECK-LABEL: {{^}}v1: 5; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xd 6define amdgpu_ps void @v1(i32 %a1) { 7entry: 8 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 9 %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 10 %2 = extractelement <4 x float> %1, i32 0 11 %3 = extractelement <4 x float> %1, i32 2 12 %4 = extractelement <4 x float> %1, i32 3 13 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4) 14 ret void 15} 16 17; CHECK-LABEL: {{^}}v2: 18; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xb 19define amdgpu_ps void @v2(i32 %a1) { 20entry: 21 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 22 %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 23 %2 = extractelement <4 x float> %1, i32 0 24 %3 = extractelement <4 x float> %1, i32 1 25 %4 = extractelement <4 x float> %1, i32 3 26 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4) 27 ret void 28} 29 30; CHECK-LABEL: {{^}}v3: 31; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xe 32define amdgpu_ps void @v3(i32 %a1) { 33entry: 34 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 35 %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 36 %2 = extractelement <4 x float> %1, i32 1 37 %3 = extractelement <4 x float> %1, i32 2 38 %4 = extractelement <4 x float> %1, i32 3 39 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4) 40 ret void 41} 42 43; CHECK-LABEL: {{^}}v4: 44; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x7 45define amdgpu_ps void @v4(i32 %a1) { 46entry: 47 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 48 %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 49 %2 = extractelement <4 x float> %1, i32 0 50 %3 = extractelement <4 x float> %1, i32 1 51 %4 = extractelement <4 x float> %1, i32 2 52 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4) 53 ret void 54} 55 56; CHECK-LABEL: {{^}}v5: 57; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xa 58define amdgpu_ps void @v5(i32 %a1) { 59entry: 60 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 61 %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 62 %2 = extractelement <4 x float> %1, i32 1 63 %3 = extractelement <4 x float> %1, i32 3 64 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3) 65 ret void 66} 67 68; CHECK-LABEL: {{^}}v6: 69; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x6 70define amdgpu_ps void @v6(i32 %a1) { 71entry: 72 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 73 %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 74 %2 = extractelement <4 x float> %1, i32 1 75 %3 = extractelement <4 x float> %1, i32 2 76 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3) 77 ret void 78} 79 80; CHECK-LABEL: {{^}}v7: 81; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x9 82define amdgpu_ps void @v7(i32 %a1) { 83entry: 84 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 85 %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 86 %2 = extractelement <4 x float> %1, i32 0 87 %3 = extractelement <4 x float> %1, i32 3 88 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3) 89 ret void 90} 91 92declare <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) readnone 93 94declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) 95