1;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s 2;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s 3 4;CHECK-LABEL: {{^}}buffer_store: 5;CHECK: buffer_store_format_xyzw v[0:3], off, s[0:3], 0 6;CHECK: buffer_store_format_xyzw v[4:7], off, s[0:3], 0 glc 7;CHECK: buffer_store_format_xyzw v[8:11], off, s[0:3], 0 slc 8define amdgpu_ps void @buffer_store(<4 x i32> inreg, <4 x float>, <4 x float>, <4 x float>) { 9main_body: 10 call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 0, i1 0, i1 0) 11 call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %2, <4 x i32> %0, i32 0, i32 0, i1 1, i1 0) 12 call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %3, <4 x i32> %0, i32 0, i32 0, i1 0, i1 1) 13 ret void 14} 15 16;CHECK-LABEL: {{^}}buffer_store_immoffs: 17;CHECK: buffer_store_format_xyzw v[0:3], off, s[0:3], 0 offset:42 18define amdgpu_ps void @buffer_store_immoffs(<4 x i32> inreg, <4 x float>) { 19main_body: 20 call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 42, i1 0, i1 0) 21 ret void 22} 23 24;CHECK-LABEL: {{^}}buffer_store_idx: 25;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen 26define amdgpu_ps void @buffer_store_idx(<4 x i32> inreg, <4 x float>, i32) { 27main_body: 28 call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i1 0, i1 0) 29 ret void 30} 31 32;CHECK-LABEL: {{^}}buffer_store_ofs: 33;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 offen 34define amdgpu_ps void @buffer_store_ofs(<4 x i32> inreg, <4 x float>, i32) { 35main_body: 36 call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 %2, i1 0, i1 0) 37 ret void 38} 39 40;CHECK-LABEL: {{^}}buffer_store_both: 41;CHECK: buffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 idxen offen 42define amdgpu_ps void @buffer_store_both(<4 x i32> inreg, <4 x float>, i32, i32) { 43main_body: 44 call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 %3, i1 0, i1 0) 45 ret void 46} 47 48;CHECK-LABEL: {{^}}buffer_store_both_reversed: 49;CHECK: v_mov_b32_e32 v6, v4 50;CHECK: buffer_store_format_xyzw v[0:3], v[5:6], s[0:3], 0 idxen offen 51define amdgpu_ps void @buffer_store_both_reversed(<4 x i32> inreg, <4 x float>, i32, i32) { 52main_body: 53 call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %3, i32 %2, i1 0, i1 0) 54 ret void 55} 56 57; Ideally, the register allocator would avoid the wait here 58; 59;CHECK-LABEL: {{^}}buffer_store_wait: 60;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen 61;CHECK: s_waitcnt vmcnt(0) expcnt(0) 62;CHECK: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen 63;CHECK: s_waitcnt vmcnt(0) 64;CHECK: buffer_store_format_xyzw v[0:3], v6, s[0:3], 0 idxen 65define amdgpu_ps void @buffer_store_wait(<4 x i32> inreg, <4 x float>, i32, i32, i32) { 66main_body: 67 call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i1 0, i1 0) 68 %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 %3, i32 0, i1 0, i1 0) 69 call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %data, <4 x i32> %0, i32 %4, i32 0, i1 0, i1 0) 70 ret void 71} 72 73;CHECK-LABEL: {{^}}buffer_store_x1: 74;CHECK: buffer_store_format_x v0, v1, s[0:3], 0 idxen 75define amdgpu_ps void @buffer_store_x1(<4 x i32> inreg %rsrc, float %data, i32 %index) { 76main_body: 77 call void @llvm.amdgcn.buffer.store.format.f32(float %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0) 78 ret void 79} 80 81;CHECK-LABEL: {{^}}buffer_store_x2: 82;CHECK: buffer_store_format_xy v[0:1], v2, s[0:3], 0 idxen 83define amdgpu_ps void @buffer_store_x2(<4 x i32> inreg %rsrc, <2 x float> %data, i32 %index) { 84main_body: 85 call void @llvm.amdgcn.buffer.store.format.v2f32(<2 x float> %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0) 86 ret void 87} 88 89declare void @llvm.amdgcn.buffer.store.format.f32(float, <4 x i32>, i32, i32, i1, i1) #0 90declare void @llvm.amdgcn.buffer.store.format.v2f32(<2 x float>, <4 x i32>, i32, i32, i1, i1) #0 91declare void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float>, <4 x i32>, i32, i32, i1, i1) #0 92declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #1 93 94attributes #0 = { nounwind } 95attributes #1 = { nounwind readonly } 96