1; RUN: llc < %s -verify-machineinstrs 2; PR8612 3; 4; This test has an inline asm with early-clobber arguments. 5; It is big enough that one of the early clobber registers is spilled. 6; 7; All the spillers would get the live ranges wrong when spilling an early 8; clobber, allowing the undef register to be allocated to the same register as 9; the early clobber. 10; 11target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32" 12target triple = "armv7-eabi" 13 14%0 = type { i32, i32 } 15 16define void @foo(i32* %in) nounwind { 17entry: 18 br label %bb.i 19 20bb.i: ; preds = %bb.i, %entry 21 br i1 undef, label %bb10.preheader.i, label %bb.i 22 23bb10.preheader.i: ; preds = %bb.i 24 br label %bb10.i 25 26bb10.i: ; preds = %bb10.i, %bb10.preheader.i 27 br i1 undef, label %bb27.i, label %bb10.i 28 29bb27.i: ; preds = %bb10.i 30 br label %bb28.i 31 32bb28.i: ; preds = %bb28.i, %bb27.i 33 br i1 undef, label %presymmetry.exit, label %bb28.i 34 35presymmetry.exit: ; preds = %bb28.i 36 %tmp175387 = or i32 undef, 12 37 %scevgep101.i = getelementptr i32, i32* %in, i32 undef 38 %tmp189401 = or i32 undef, 7 39 %scevgep97.i = getelementptr i32, i32* %in, i32 undef 40 %tmp198410 = or i32 undef, 1 41 %scevgep.i48 = getelementptr i32, i32* %in, i32 undef 42 %0 = load i32, i32* %scevgep.i48, align 4 43 %1 = add nsw i32 %0, 0 44 store i32 %1, i32* undef, align 4 45 %asmtmp.i.i33.i.i.i = tail call %0 asm "smull\09$0, $1, $2, $3", "=&r,=&r,%r,r,~{cc}"(i32 undef, i32 1518500250) nounwind 46 %asmresult1.i.i34.i.i.i = extractvalue %0 %asmtmp.i.i33.i.i.i, 1 47 %2 = shl i32 %asmresult1.i.i34.i.i.i, 1 48 %3 = load i32, i32* null, align 4 49 %4 = load i32, i32* undef, align 4 50 %5 = sub nsw i32 %3, %4 51 %6 = load i32, i32* undef, align 4 52 %7 = load i32, i32* null, align 4 53 %8 = sub nsw i32 %6, %7 54 %9 = load i32, i32* %scevgep97.i, align 4 55 %10 = load i32, i32* undef, align 4 56 %11 = sub nsw i32 %9, %10 57 %12 = load i32, i32* null, align 4 58 %13 = load i32, i32* %scevgep101.i, align 4 59 %14 = sub nsw i32 %12, %13 60 %15 = load i32, i32* %scevgep.i48, align 4 61 %16 = load i32, i32* null, align 4 62 %17 = add nsw i32 %16, %15 63 %18 = sub nsw i32 %15, %16 64 %19 = load i32, i32* undef, align 4 65 %20 = add nsw i32 %19, %2 66 %21 = sub nsw i32 %19, %2 67 %22 = add nsw i32 %14, %5 68 %23 = sub nsw i32 %5, %14 69 %24 = add nsw i32 %11, %8 70 %25 = sub nsw i32 %8, %11 71 %26 = add nsw i32 %21, %23 72 store i32 %26, i32* %scevgep.i48, align 4 73 %27 = sub nsw i32 %25, %18 74 store i32 %27, i32* null, align 4 75 %28 = sub nsw i32 %23, %21 76 store i32 %28, i32* undef, align 4 77 %29 = add nsw i32 %18, %25 78 store i32 %29, i32* undef, align 4 79 %30 = add nsw i32 %17, %22 80 store i32 %30, i32* %scevgep101.i, align 4 81 %31 = add nsw i32 %20, %24 82 store i32 %31, i32* null, align 4 83 unreachable 84} 85