1; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE 2; RUN: llc -mtriple=armeb-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE 3 4; 171 = 0x000000ab 5define i64 @f1(i64 %a) { 6; CHECK: f1 7; CHECK-LE: subs r0, r0, #171 8; CHECK-LE: sbc r1, r1, #0 9; CHECK-BE: subs r1, r1, #171 10; CHECK-BE: sbc r0, r0, #0 11 %tmp = sub i64 %a, 171 12 ret i64 %tmp 13} 14 15; 66846720 = 0x03fc0000 16define i64 @f2(i64 %a) { 17; CHECK: f2 18; CHECK-LE: subs r0, r0, #66846720 19; CHECK-LE: sbc r1, r1, #0 20; CHECK-BE: subs r1, r1, #66846720 21; CHECK-BE: sbc r0, r0, #0 22 %tmp = sub i64 %a, 66846720 23 ret i64 %tmp 24} 25 26; 734439407618 = 0x000000ab00000002 27define i64 @f3(i64 %a) { 28; CHECK: f3 29; CHECK-LE: subs r0, r0, #2 30; CHECK-LE: sbc r1, r1, #171 31; CHECK-BE: subs r1, r1, #2 32; CHECK-BE: sbc r0, r0, #171 33 %tmp = sub i64 %a, 734439407618 34 ret i64 %tmp 35} 36 37define i32 @f4(i32 %x) { 38entry: 39; CHECK: f4 40; CHECK: rsbs 41 %sub = sub i32 1, %x 42 %cmp = icmp ugt i32 %sub, 0 43 %sel = select i1 %cmp, i32 1, i32 %sub 44 ret i32 %sel 45} 46 47; rdar://11726136 48define i32 @f5(i32 %x) { 49entry: 50; CHECK: f5 51; CHECK: movw r1, #65535 52; CHECK-NOT: movt 53; CHECK-NOT: add 54; CHECK: sub r0, r0, r1 55 %sub = add i32 %x, -65535 56 ret i32 %sub 57} 58