1; RUN: llc -march=hexagon -mcpu=hexagonv60 -O2 -enable-hexagon-hvx < %s | FileCheck %s 2 3; CHECK: vmem(r{{[0-9]+}}+#3) = v{{[0-9]+}} 4; CHECK: call puts 5; CHECK: call print_vecpred 6; CHECK: v{{[0-9]+}}{{ *}}={{ *}}vmem(r{{[0-9]+}}+#3) 7 8target triple = "hexagon" 9 10@K = global i64 0, align 8 11@src = global i32 -1, align 4 12@Q6VecPredResult = common global <16 x i32> zeroinitializer, align 64 13@dst_addresses = common global [15 x i64] zeroinitializer, align 8 14@ptr_addresses = common global [15 x i8*] zeroinitializer, align 8 15@src_addresses = common global [15 x i8*] zeroinitializer, align 8 16@ptr = common global [32768 x i32] zeroinitializer, align 8 17@vecpreds = common global [15 x <16 x i32>] zeroinitializer, align 64 18@VectorResult = common global <16 x i32> zeroinitializer, align 64 19@vectors = common global [15 x <16 x i32>] zeroinitializer, align 64 20@VectorPairResult = common global <32 x i32> zeroinitializer, align 128 21@vector_pairs = common global [15 x <32 x i32>] zeroinitializer, align 128 22@str = private unnamed_addr constant [106 x i8] c"Q6VecPred4 : Q6_Q_vandor_QVR(Q6_Q_vand_VR(Q6_V_vsplat_R(1+1),(0x01010101)),Q6_V_vsplat_R(0+1),INT32_MIN)\00" 23@str3 = private unnamed_addr constant [99 x i8] c"Q6VecPred4 : Q6_Q_vandor_QVR(Q6_Q_vand_VR(Q6_V_vsplat_R(1+1),(0x01010101)),Q6_V_vsplat_R(0+1),-1)\00" 24@str4 = private unnamed_addr constant [98 x i8] c"Q6VecPred4 : Q6_Q_vandor_QVR(Q6_Q_vand_VR(Q6_V_vsplat_R(1+1),(0x01010101)),Q6_V_vsplat_R(0+1),0)\00" 25 26; Function Attrs: nounwind 27define i32 @main() #0 { 28entry: 29 %call = tail call i32 bitcast (i32 (...)* @init_addresses to i32 ()*)() #3 30 %call1 = tail call i32 @acquire_vector_unit(i8 zeroext 0) #3 31 tail call void @init_vectors() #3 32 %0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 2) 33 %1 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %0, i32 16843009) 34 %2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) 35 %3 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt.acc(<512 x i1> %1, <16 x i32> %2, i32 -2147483648) 36 %4 = bitcast <512 x i1> %3 to <16 x i32> 37 store <16 x i32> %4, <16 x i32>* @Q6VecPredResult, align 64, !tbaa !1 38 %puts = tail call i32 @puts(i8* getelementptr inbounds ([106 x i8], [106 x i8]* @str, i32 0, i32 0)) 39 tail call void @print_vecpred(i32 512, i8* bitcast (<16 x i32>* @Q6VecPredResult to i8*)) #3 40 %5 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt.acc(<512 x i1> %1, <16 x i32> %2, i32 -1) 41 %6 = bitcast <512 x i1> %5 to <16 x i32> 42 store <16 x i32> %6, <16 x i32>* @Q6VecPredResult, align 64, !tbaa !1 43 %puts5 = tail call i32 @puts(i8* getelementptr inbounds ([99 x i8], [99 x i8]* @str3, i32 0, i32 0)) 44 tail call void @print_vecpred(i32 512, i8* bitcast (<16 x i32>* @Q6VecPredResult to i8*)) #3 45 %7 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt.acc(<512 x i1> %1, <16 x i32> %2, i32 0) 46 %8 = bitcast <512 x i1> %7 to <16 x i32> 47 store <16 x i32> %8, <16 x i32>* @Q6VecPredResult, align 64, !tbaa !1 48 %puts6 = tail call i32 @puts(i8* getelementptr inbounds ([98 x i8], [98 x i8]* @str4, i32 0, i32 0)) 49 tail call void @print_vecpred(i32 512, i8* bitcast (<16 x i32>* @Q6VecPredResult to i8*)) #3 50 ret i32 0 51} 52 53declare i32 @init_addresses(...) #1 54 55declare i32 @acquire_vector_unit(i8 zeroext) #1 56 57declare void @init_vectors() #1 58 59; Function Attrs: nounwind readnone 60declare <512 x i1> @llvm.hexagon.V6.vandvrt.acc(<512 x i1>, <16 x i32>, i32) #2 61 62; Function Attrs: nounwind readnone 63declare <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #2 64 65; Function Attrs: nounwind readnone 66declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #2 67 68declare void @print_vecpred(i32, i8*) #1 69 70; Function Attrs: nounwind 71declare i32 @puts(i8* nocapture readonly) #3 72 73attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } 74attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } 75attributes #2 = { nounwind readnone } 76attributes #3 = { nounwind } 77 78!1 = !{!2, !2, i64 0} 79!2 = !{!"omnipotent char", !3, i64 0} 80!3 = !{!"Simple C/C++ TBAA"} 81