1; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefixes=ALL,GP32 2; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,GP32 3; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefixes=ALL,GP32 4; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefixes=ALL,GP32 5; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefixes=ALL,GP32 6; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,GP32 7; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s -check-prefixes=ALL,GP64 8; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefixes=ALL,GP64 9; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,GP64 10; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,GP64 11; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s -check-prefixes=ALL,GP64 12; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s -check-prefixes=ALL,GP64 13; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GP64 14; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ 15; RUN: -check-prefixes=ALL,MM,MM32 16; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ 17; RUN: -check-prefixes=ALL,MM,MM32 18; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \ 19; RUN: -check-prefixes=ALL,MM,MM64 20 21define signext i1 @or_i1(i1 signext %a, i1 signext %b) { 22entry: 23; ALL-LABEL: or_i1: 24 25 ; GP32: or $2, $4, $5 26 27 ; GP64: or $2, $4, $5 28 29 ; MM: or16 $[[T0:[0-9]+]], $5 30 ; MM: move $2, $[[T0]] 31 32 %r = or i1 %a, %b 33 ret i1 %r 34} 35 36define signext i8 @or_i8(i8 signext %a, i8 signext %b) { 37entry: 38; ALL-LABEL: or_i8: 39 40 ; GP32: or $2, $4, $5 41 42 ; GP64: or $2, $4, $5 43 44 ; MM: or16 $[[T0:[0-9]+]], $5 45 ; MM: move $2, $[[T0]] 46 47 %r = or i8 %a, %b 48 ret i8 %r 49} 50 51define signext i16 @or_i16(i16 signext %a, i16 signext %b) { 52entry: 53; ALL-LABEL: or_i16: 54 55 ; GP32: or $2, $4, $5 56 57 ; GP64: or $2, $4, $5 58 59 ; MM: or16 $[[T0:[0-9]+]], $5 60 ; MM: move $2, $[[T0]] 61 62 %r = or i16 %a, %b 63 ret i16 %r 64} 65 66define signext i32 @or_i32(i32 signext %a, i32 signext %b) { 67entry: 68; ALL-LABEL: or_i32: 69 70 ; GP32: or $2, $4, $5 71 72 ; GP64: or $[[T0:[0-9]+]], $4, $5 73 ; FIXME: The sll instruction below is redundant. 74 ; GP64: sll $2, $[[T0]], 0 75 76 ; MM32: or16 $[[T0:[0-9]+]], $5 77 ; MM32: move $2, $[[T0]] 78 79 ; MM64: or $[[T0:[0-9]+]], $4, $5 80 ; MM64: sll $2, $[[T0]], 0 81 82 %r = or i32 %a, %b 83 ret i32 %r 84} 85 86define signext i64 @or_i64(i64 signext %a, i64 signext %b) { 87entry: 88; ALL-LABEL: or_i64: 89 90 ; GP32: or $2, $4, $6 91 ; GP32: or $3, $5, $7 92 93 ; GP64: or $2, $4, $5 94 95 ; MM32: or16 $[[T0:[0-9]+]], $6 96 ; MM32: or16 $[[T1:[0-9]+]], $7 97 ; MM32: move $2, $[[T0]] 98 ; MM32: move $3, $[[T1]] 99 100 ; MM64: or $2, $4, $5 101 102 %r = or i64 %a, %b 103 ret i64 %r 104} 105 106define signext i128 @or_i128(i128 signext %a, i128 signext %b) { 107entry: 108; ALL-LABEL: or_i128: 109 110 ; GP32: lw $[[T0:[0-9]+]], 24($sp) 111 ; GP32: lw $[[T1:[0-9]+]], 20($sp) 112 ; GP32: lw $[[T2:[0-9]+]], 16($sp) 113 ; GP32: or $2, $4, $[[T2]] 114 ; GP32: or $3, $5, $[[T1]] 115 ; GP32: or $4, $6, $[[T0]] 116 ; GP32: lw $[[T3:[0-9]+]], 28($sp) 117 ; GP32: or $5, $7, $[[T3]] 118 119 ; GP64: or $2, $4, $6 120 ; GP64: or $3, $5, $7 121 122 ; MM32: lw $[[T0:[0-9]+]], 20($sp) 123 ; MM32: lw $[[T1:[0-9]+]], 16($sp) 124 ; MM32: or16 $[[T1]], $4 125 ; MM32: or16 $[[T0]], $5 126 ; MM32: lw $[[T2:[0-9]+]], 24($sp) 127 ; MM32: or16 $[[T2]], $6 128 ; MM32: lw $[[T3:[0-9]+]], 28($sp) 129 ; MM32: or16 $[[T3]], $7 130 131 ; MM64: or $2, $4, $6 132 ; MM64: or $3, $5, $7 133 134 %r = or i128 %a, %b 135 ret i128 %r 136} 137 138define signext i1 @or_i1_4(i1 signext %b) { 139entry: 140; ALL-LABEL: or_i1_4: 141 142 ; ALL: move $2, $4 143 144 %r = or i1 4, %b 145 ret i1 %r 146} 147 148define signext i8 @or_i8_4(i8 signext %b) { 149entry: 150; ALL-LABEL: or_i8_4: 151 152 ; ALL: ori $2, $4, 4 153 154 %r = or i8 4, %b 155 ret i8 %r 156} 157 158define signext i16 @or_i16_4(i16 signext %b) { 159entry: 160; ALL-LABEL: or_i16_4: 161 162 ; ALL: ori $2, $4, 4 163 164 %r = or i16 4, %b 165 ret i16 %r 166} 167 168define signext i32 @or_i32_4(i32 signext %b) { 169entry: 170; ALL-LABEL: or_i32_4: 171 172 ; ALL: ori $2, $4, 4 173 174 %r = or i32 4, %b 175 ret i32 %r 176} 177 178define signext i64 @or_i64_4(i64 signext %b) { 179entry: 180; ALL-LABEL: or_i64_4: 181 182 ; GP32: ori $3, $5, 4 183 ; GP32: move $2, $4 184 185 ; GP64: ori $2, $4, 4 186 187 ; MM32: ori $3, $5, 4 188 ; MM32: move $2, $4 189 190 ; MM64: ori $2, $4, 4 191 192 %r = or i64 4, %b 193 ret i64 %r 194} 195 196define signext i128 @or_i128_4(i128 signext %b) { 197entry: 198; ALL-LABEL: or_i128_4: 199 200 ; GP32: ori $[[T0:[0-9]+]], $7, 4 201 ; GP32: move $2, $4 202 ; GP32: move $3, $5 203 ; GP32: move $4, $6 204 ; GP32: move $5, $[[T0]] 205 206 ; GP64: ori $3, $5, 4 207 ; GP64: move $2, $4 208 209 ; MM32: ori $[[T0:[0-9]+]], $7, 4 210 ; MM32: move $2, $4 211 ; MM32: move $3, $5 212 ; MM32: move $4, $6 213 ; MM32: move $5, $[[T0]] 214 215 ; MM64: ori $3, $5, 4 216 ; MM64: move $2, $4 217 218 %r = or i128 4, %b 219 ret i128 %r 220} 221 222define signext i1 @or_i1_31(i1 signext %b) { 223entry: 224; ALL-LABEL: or_i1_31: 225 226 ; GP32: addiu $2, $zero, -1 227 228 ; GP64: addiu $2, $zero, -1 229 230 ; MM: li16 $2, -1 231 232 %r = or i1 31, %b 233 ret i1 %r 234} 235 236define signext i8 @or_i8_31(i8 signext %b) { 237entry: 238; ALL-LABEL: or_i8_31: 239 240 ; ALL: ori $2, $4, 31 241 242 %r = or i8 31, %b 243 ret i8 %r 244} 245 246define signext i16 @or_i16_31(i16 signext %b) { 247entry: 248; ALL-LABEL: or_i16_31: 249 250 ; ALL: ori $2, $4, 31 251 252 %r = or i16 31, %b 253 ret i16 %r 254} 255 256define signext i32 @or_i32_31(i32 signext %b) { 257entry: 258; ALL-LABEL: or_i32_31: 259 260 ; ALL: ori $2, $4, 31 261 262 %r = or i32 31, %b 263 ret i32 %r 264} 265 266define signext i64 @or_i64_31(i64 signext %b) { 267entry: 268; ALL-LABEL: or_i64_31: 269 270 ; GP32: ori $3, $5, 31 271 ; GP32: move $2, $4 272 273 ; GP64: ori $2, $4, 31 274 275 ; MM32: ori $3, $5, 31 276 ; MM32: move $2, $4 277 278 ; MM64: ori $2, $4, 31 279 280 %r = or i64 31, %b 281 ret i64 %r 282} 283 284define signext i128 @or_i128_31(i128 signext %b) { 285entry: 286; ALL-LABEL: or_i128_31: 287 288 ; GP32: ori $[[T0:[0-9]+]], $7, 31 289 ; GP32: move $2, $4 290 ; GP32: move $3, $5 291 ; GP32: move $4, $6 292 ; GP32: move $5, $[[T0]] 293 294 ; GP64: ori $3, $5, 31 295 ; GP64: move $2, $4 296 297 ; MM32: ori $[[T0:[0-9]+]], $7, 31 298 ; MM32: move $2, $4 299 ; MM32: move $3, $5 300 ; MM32: move $4, $6 301 ; MM32: move $5, $[[T0]] 302 303 ; MM64: ori $3, $5, 31 304 ; MM64: move $2, $4 305 306 %r = or i128 31, %b 307 ret i128 %r 308} 309 310define signext i1 @or_i1_255(i1 signext %b) { 311entry: 312; ALL-LABEL: or_i1_255: 313 314 ; GP32: addiu $2, $zero, -1 315 316 ; GP64: addiu $2, $zero, -1 317 318 ; MM: li16 $2, -1 319 320 %r = or i1 255, %b 321 ret i1 %r 322} 323 324define signext i8 @or_i8_255(i8 signext %b) { 325entry: 326; ALL-LABEL: or_i8_255: 327 328 ; GP32: addiu $2, $zero, -1 329 330 ; GP64: addiu $2, $zero, -1 331 332 ; MM: li16 $2, -1 333 334 %r = or i8 255, %b 335 ret i8 %r 336} 337 338define signext i16 @or_i16_255(i16 signext %b) { 339entry: 340; ALL-LABEL: or_i16_255: 341 342 ; ALL: ori $2, $4, 255 343 344 %r = or i16 255, %b 345 ret i16 %r 346} 347 348define signext i32 @or_i32_255(i32 signext %b) { 349entry: 350; ALL-LABEL: or_i32_255: 351 352 ; ALL: ori $2, $4, 255 353 354 %r = or i32 255, %b 355 ret i32 %r 356} 357 358define signext i64 @or_i64_255(i64 signext %b) { 359entry: 360; ALL-LABEL: or_i64_255: 361 362 ; GP32: ori $3, $5, 255 363 ; GP32: move $2, $4 364 365 ; GP64: ori $2, $4, 255 366 367 ; MM32: ori $3, $5, 255 368 ; MM32: move $2, $4 369 370 ; MM64: ori $2, $4, 255 371 372 %r = or i64 255, %b 373 ret i64 %r 374} 375 376define signext i128 @or_i128_255(i128 signext %b) { 377entry: 378; ALL-LABEL: or_i128_255: 379 380 ; GP32: ori $[[T0:[0-9]+]], $7, 255 381 ; GP32: move $2, $4 382 ; GP32: move $3, $5 383 ; GP32: move $4, $6 384 ; GP32: move $5, $[[T0]] 385 386 ; GP64: ori $3, $5, 255 387 ; GP64: move $2, $4 388 389 ; MM32: ori $[[T0:[0-9]+]], $7, 255 390 ; MM32: move $2, $4 391 ; MM32: move $3, $5 392 ; MM32: move $4, $6 393 ; MM32: move $5, $[[T0]] 394 395 ; MM64: ori $3, $5, 255 396 ; MM64: move $2, $4 397 398 %r = or i128 255, %b 399 ret i128 %r 400} 401 402define signext i1 @or_i1_32768(i1 signext %b) { 403entry: 404; ALL-LABEL: or_i1_32768: 405 406 ; ALL: move $2, $4 407 408 %r = or i1 32768, %b 409 ret i1 %r 410} 411 412define signext i8 @or_i8_32768(i8 signext %b) { 413entry: 414; ALL-LABEL: or_i8_32768: 415 416 ; ALL: move $2, $4 417 418 %r = or i8 32768, %b 419 ret i8 %r 420} 421 422define signext i16 @or_i16_32768(i16 signext %b) { 423entry: 424; ALL-LABEL: or_i16_32768: 425 426 ; GP32: addiu $[[T0:[0-9]+]], $zero, -32768 427 ; GP32: or $2, $4, $[[T0]] 428 429 ; GP64: addiu $[[T0:[0-9]+]], $zero, -32768 430 ; GP64: or $2, $4, $[[T0]] 431 432 ; MM: addiu $2, $zero, -32768 433 ; MM: or16 $2, $4 434 435 %r = or i16 32768, %b 436 ret i16 %r 437} 438 439define signext i32 @or_i32_32768(i32 signext %b) { 440entry: 441; ALL-LABEL: or_i32_32768: 442 443 ; ALL: ori $2, $4, 32768 444 445 %r = or i32 32768, %b 446 ret i32 %r 447} 448 449define signext i64 @or_i64_32768(i64 signext %b) { 450entry: 451; ALL-LABEL: or_i64_32768: 452 453 ; GP32: ori $3, $5, 32768 454 ; GP32: move $2, $4 455 456 ; GP64: ori $2, $4, 32768 457 458 ; MM32: ori $3, $5, 32768 459 ; MM32: move $2, $4 460 461 ; MM64: ori $2, $4, 32768 462 463 %r = or i64 32768, %b 464 ret i64 %r 465} 466 467define signext i128 @or_i128_32768(i128 signext %b) { 468entry: 469; ALL-LABEL: or_i128_32768: 470 471 ; GP32: ori $[[T0:[0-9]+]], $7, 32768 472 ; GP32: move $2, $4 473 ; GP32: move $3, $5 474 ; GP32: move $4, $6 475 ; GP32: move $5, $[[T0]] 476 477 ; GP64: ori $3, $5, 32768 478 ; GP64: move $2, $4 479 480 ; MM32: ori $[[T0:[0-9]+]], $7, 32768 481 ; MM32: move $2, $4 482 ; MM32: move $3, $5 483 ; MM32: move $4, $6 484 ; MM32: move $5, $[[T0]] 485 486 ; MM64: ori $3, $5, 32768 487 ; MM64: move $2, $4 488 489 %r = or i128 32768, %b 490 ret i128 %r 491} 492 493define signext i1 @or_i1_65(i1 signext %b) { 494entry: 495; ALL-LABEL: or_i1_65: 496 497 ; GP32: addiu $2, $zero, -1 498 499 ; GP64: addiu $2, $zero, -1 500 501 ; MM: li16 $2, -1 502 503 %r = or i1 65, %b 504 ret i1 %r 505} 506 507define signext i8 @or_i8_65(i8 signext %b) { 508entry: 509; ALL-LABEL: or_i8_65: 510 511 ; ALL: ori $2, $4, 65 512 513 %r = or i8 65, %b 514 ret i8 %r 515} 516 517define signext i16 @or_i16_65(i16 signext %b) { 518entry: 519; ALL-LABEL: or_i16_65: 520 521 ; ALL: ori $2, $4, 65 522 523 %r = or i16 65, %b 524 ret i16 %r 525} 526 527define signext i32 @or_i32_65(i32 signext %b) { 528entry: 529; ALL-LABEL: or_i32_65: 530 531 ; ALL: ori $2, $4, 65 532 533 %r = or i32 65, %b 534 ret i32 %r 535} 536 537define signext i64 @or_i64_65(i64 signext %b) { 538entry: 539; ALL-LABEL: or_i64_65: 540 541 ; GP32: ori $3, $5, 65 542 ; GP32: move $2, $4 543 544 ; GP64: ori $2, $4, 65 545 546 ; MM32: ori $3, $5, 65 547 ; MM32: move $2, $4 548 549 ; MM64: ori $2, $4, 65 550 551 %r = or i64 65, %b 552 ret i64 %r 553} 554 555define signext i128 @or_i128_65(i128 signext %b) { 556entry: 557; ALL-LABEL: or_i128_65: 558 559 ; GP32: ori $[[T0:[0-9]+]], $7, 65 560 ; GP32: move $2, $4 561 ; GP32: move $3, $5 562 ; GP32: move $4, $6 563 ; GP32: move $5, $[[T0]] 564 565 ; GP64: ori $3, $5, 65 566 ; GP64: move $2, $4 567 568 ; MM32: ori $[[T0:[0-9]+]], $7, 65 569 ; MM32: move $2, $4 570 ; MM32: move $3, $5 571 ; MM32: move $4, $6 572 ; MM32: move $5, $[[T0]] 573 574 ; MM64: ori $3, $5, 65 575 ; MM64: move $2, $4 576 577 %r = or i128 65, %b 578 ret i128 %r 579} 580 581define signext i1 @or_i1_256(i1 signext %b) { 582entry: 583; ALL-LABEL: or_i1_256: 584 585 ; ALL: move $2, $4 586 587 %r = or i1 256, %b 588 ret i1 %r 589} 590 591define signext i8 @or_i8_256(i8 signext %b) { 592entry: 593; ALL-LABEL: or_i8_256: 594 595 ; ALL: move $2, $4 596 597 %r = or i8 256, %b 598 ret i8 %r 599} 600 601define signext i16 @or_i16_256(i16 signext %b) { 602entry: 603; ALL-LABEL: or_i16_256: 604 605 ; ALL: ori $2, $4, 256 606 607 %r = or i16 256, %b 608 ret i16 %r 609} 610 611define signext i32 @or_i32_256(i32 signext %b) { 612entry: 613; ALL-LABEL: or_i32_256: 614 615 ; ALL: ori $2, $4, 256 616 617 %r = or i32 256, %b 618 ret i32 %r 619} 620 621define signext i64 @or_i64_256(i64 signext %b) { 622entry: 623; ALL-LABEL: or_i64_256: 624 625 ; GP32: ori $3, $5, 256 626 ; GP32: move $2, $4 627 628 ; GP64: ori $2, $4, 256 629 630 ; MM32: ori $3, $5, 256 631 ; MM32: move $2, $4 632 633 ; MM64: ori $2, $4, 256 634 635 %r = or i64 256, %b 636 ret i64 %r 637} 638 639define signext i128 @or_i128_256(i128 signext %b) { 640entry: 641; ALL-LABEL: or_i128_256: 642 643 ; GP32: ori $[[T0:[0-9]+]], $7, 256 644 ; GP32: move $2, $4 645 ; GP32: move $3, $5 646 ; GP32: move $4, $6 647 ; GP32: move $5, $[[T0]] 648 649 ; GP64: ori $3, $5, 256 650 ; GP64: move $2, $4 651 652 ; MM32: ori $[[T0:[0-9]+]], $7, 256 653 ; MM32: move $2, $4 654 ; MM32: move $3, $5 655 ; MM32: move $4, $6 656 ; MM32: move $5, $[[T0]] 657 658 ; MM64: ori $3, $5, 256 659 ; MM64: move $2, $4 660 661 %r = or i128 256, %b 662 ret i128 %r 663} 664