1; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips \ 2; RUN: -relocation-model=pic < %s | \ 3; RUN: FileCheck %s -check-prefixes=ALL,MM32 4; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips \ 5; RUN: -relocation-model=pic < %s | \ 6; RUN: FileCheck %s -check-prefixes=ALL,MM32 7; RUN: llc -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 \ 8; RUN: -relocation-model=pic < %s | \ 9; RUN: FileCheck %s -check-prefixes=ALL,MM64 10 11@gf0 = external global float 12 13define float @test_lwc1() { 14entry: 15; CHECK-LABEL: test_lwc1 16; MM32: lui $[[R0:[0-9]+]], %hi(_gp_disp) 17; MM32: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp) 18; MM32: addu $[[R2:[0-9]+]], $[[R1]], $25 19; MM32: lw $[[R3:[0-9]+]], %got(gf0)($[[R2]]) 20; MM32: lwc1 $f0, 0($[[R3]]) 21 22; MM64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test_lwc1))) 23; MM64: daddu $[[R1:[0-9]+]], $[[R0]], $25 24; MM64: daddiu $[[R2:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test_lwc1))) 25; MM64: ld $[[R3:[0-9]+]], %got_disp(gf0)($[[R2]]) 26; MM64: lwc1 $f0, 0($[[R3]]) 27 28 %0 = load float, float* @gf0, align 4 29 ret float %0 30} 31 32define void @test_swc1(float %a) { 33entry: 34; CHECK-LABEL: test_swc1 35; MM32: lui $[[R0:[0-9]+]], %hi(_gp_disp) 36; MM32: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp) 37; MM32: addu $[[R2:[0-9]+]], $[[R1]], $25 38; MM32: lw $[[R3:[0-9]+]], %got(gf0)($[[R2]]) 39; MM32: swc1 $f12, 0($[[R3]]) 40 41; MM64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test_swc1))) 42; MM64: daddu $[[R1:[0-9]+]], $[[R0]], $25 43; MM64: daddiu $[[R2:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test_swc1))) 44; MM64: ld $[[R3:[0-9]+]], %got_disp(gf0)($[[R2]]) 45; MM64: swc1 $f12, 0($[[R3]]) 46 47 store float %a, float* @gf0, align 4 48 ret void 49} 50 51