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1; Test the MSA floating point to integer intrinsics that are encoded with the
2; 2RF instruction format. This includes conversions but other instructions such
3; as fclass are also here.
4
5; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s
6; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s
7
8@llvm_mips_fclass_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
9@llvm_mips_fclass_w_RES  = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
10
11define void @llvm_mips_fclass_w_test() nounwind {
12entry:
13  %0 = load <4 x float>, <4 x float>* @llvm_mips_fclass_w_ARG1
14  %1 = tail call <4 x i32> @llvm.mips.fclass.w(<4 x float> %0)
15  store <4 x i32> %1, <4 x i32>* @llvm_mips_fclass_w_RES
16  ret void
17}
18
19declare <4 x i32> @llvm.mips.fclass.w(<4 x float>) nounwind
20
21; CHECK: llvm_mips_fclass_w_test:
22; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_fclass_w_ARG1)
23; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
24; CHECK-DAG: fclass.w [[WD:\$w[0-9]+]], [[WS]]
25; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_fclass_w_RES)
26; CHECK-DAG: st.w [[WD]], 0([[R2]])
27; CHECK: .size llvm_mips_fclass_w_test
28;
29@llvm_mips_fclass_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
30@llvm_mips_fclass_d_RES  = global <2 x i64> <i64 0, i64 0>, align 16
31
32define void @llvm_mips_fclass_d_test() nounwind {
33entry:
34  %0 = load <2 x double>, <2 x double>* @llvm_mips_fclass_d_ARG1
35  %1 = tail call <2 x i64> @llvm.mips.fclass.d(<2 x double> %0)
36  store <2 x i64> %1, <2 x i64>* @llvm_mips_fclass_d_RES
37  ret void
38}
39
40declare <2 x i64> @llvm.mips.fclass.d(<2 x double>) nounwind
41
42; CHECK: llvm_mips_fclass_d_test:
43; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_fclass_d_ARG1)
44; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
45; CHECK-DAG: fclass.d [[WD:\$w[0-9]+]], [[WS]]
46; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_fclass_d_RES)
47; CHECK-DAG: st.d [[WD]], 0([[R2]])
48; CHECK: .size llvm_mips_fclass_d_test
49;
50@llvm_mips_ftrunc_s_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
51@llvm_mips_ftrunc_s_w_RES  = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
52
53define void @llvm_mips_ftrunc_s_w_test() nounwind {
54entry:
55  %0 = load <4 x float>, <4 x float>* @llvm_mips_ftrunc_s_w_ARG1
56  %1 = tail call <4 x i32> @llvm.mips.ftrunc.s.w(<4 x float> %0)
57  store <4 x i32> %1, <4 x i32>* @llvm_mips_ftrunc_s_w_RES
58  ret void
59}
60
61declare <4 x i32> @llvm.mips.ftrunc.s.w(<4 x float>) nounwind
62
63; CHECK: llvm_mips_ftrunc_s_w_test:
64; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftrunc_s_w_ARG1)
65; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
66; CHECK-DAG: ftrunc_s.w [[WD:\$w[0-9]+]], [[WS]]
67; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftrunc_s_w_RES)
68; CHECK-DAG: st.w [[WD]], 0([[R2]])
69; CHECK: .size llvm_mips_ftrunc_s_w_test
70;
71@llvm_mips_ftrunc_s_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
72@llvm_mips_ftrunc_s_d_RES  = global <2 x i64> <i64 0, i64 0>, align 16
73
74define void @llvm_mips_ftrunc_s_d_test() nounwind {
75entry:
76  %0 = load <2 x double>, <2 x double>* @llvm_mips_ftrunc_s_d_ARG1
77  %1 = tail call <2 x i64> @llvm.mips.ftrunc.s.d(<2 x double> %0)
78  store <2 x i64> %1, <2 x i64>* @llvm_mips_ftrunc_s_d_RES
79  ret void
80}
81
82declare <2 x i64> @llvm.mips.ftrunc.s.d(<2 x double>) nounwind
83
84; CHECK: llvm_mips_ftrunc_s_d_test:
85; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftrunc_s_d_ARG1)
86; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
87; CHECK-DAG: ftrunc_s.d [[WD:\$w[0-9]+]], [[WS]]
88; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftrunc_s_d_RES)
89; CHECK-DAG: st.d [[WD]], 0([[R2]])
90; CHECK: .size llvm_mips_ftrunc_s_d_test
91;
92@llvm_mips_ftrunc_u_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
93@llvm_mips_ftrunc_u_w_RES  = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
94
95define void @llvm_mips_ftrunc_u_w_test() nounwind {
96entry:
97  %0 = load <4 x float>, <4 x float>* @llvm_mips_ftrunc_u_w_ARG1
98  %1 = tail call <4 x i32> @llvm.mips.ftrunc.u.w(<4 x float> %0)
99  store <4 x i32> %1, <4 x i32>* @llvm_mips_ftrunc_u_w_RES
100  ret void
101}
102
103declare <4 x i32> @llvm.mips.ftrunc.u.w(<4 x float>) nounwind
104
105; CHECK: llvm_mips_ftrunc_u_w_test:
106; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftrunc_u_w_ARG1)
107; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
108; CHECK-DAG: ftrunc_u.w [[WD:\$w[0-9]+]], [[WS]]
109; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftrunc_u_w_RES)
110; CHECK-DAG: st.w [[WD]], 0([[R2]])
111; CHECK: .size llvm_mips_ftrunc_u_w_test
112;
113@llvm_mips_ftrunc_u_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
114@llvm_mips_ftrunc_u_d_RES  = global <2 x i64> <i64 0, i64 0>, align 16
115
116define void @llvm_mips_ftrunc_u_d_test() nounwind {
117entry:
118  %0 = load <2 x double>, <2 x double>* @llvm_mips_ftrunc_u_d_ARG1
119  %1 = tail call <2 x i64> @llvm.mips.ftrunc.u.d(<2 x double> %0)
120  store <2 x i64> %1, <2 x i64>* @llvm_mips_ftrunc_u_d_RES
121  ret void
122}
123
124declare <2 x i64> @llvm.mips.ftrunc.u.d(<2 x double>) nounwind
125
126; CHECK: llvm_mips_ftrunc_u_d_test:
127; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftrunc_u_d_ARG1)
128; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
129; CHECK-DAG: ftrunc_u.d [[WD:\$w[0-9]+]], [[WS]]
130; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftrunc_u_d_RES)
131; CHECK-DAG: st.d [[WD]], 0([[R2]])
132; CHECK: .size llvm_mips_ftrunc_u_d_test
133;
134@llvm_mips_ftint_s_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
135@llvm_mips_ftint_s_w_RES  = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
136
137define void @llvm_mips_ftint_s_w_test() nounwind {
138entry:
139  %0 = load <4 x float>, <4 x float>* @llvm_mips_ftint_s_w_ARG1
140  %1 = tail call <4 x i32> @llvm.mips.ftint.s.w(<4 x float> %0)
141  store <4 x i32> %1, <4 x i32>* @llvm_mips_ftint_s_w_RES
142  ret void
143}
144
145declare <4 x i32> @llvm.mips.ftint.s.w(<4 x float>) nounwind
146
147; CHECK: llvm_mips_ftint_s_w_test:
148; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftint_s_w_ARG1)
149; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
150; CHECK-DAG: ftint_s.w [[WD:\$w[0-9]+]], [[WS]]
151; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftint_s_w_RES)
152; CHECK-DAG: st.w [[WD]], 0([[R2]])
153; CHECK: .size llvm_mips_ftint_s_w_test
154;
155@llvm_mips_ftint_s_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
156@llvm_mips_ftint_s_d_RES  = global <2 x i64> <i64 0, i64 0>, align 16
157
158define void @llvm_mips_ftint_s_d_test() nounwind {
159entry:
160  %0 = load <2 x double>, <2 x double>* @llvm_mips_ftint_s_d_ARG1
161  %1 = tail call <2 x i64> @llvm.mips.ftint.s.d(<2 x double> %0)
162  store <2 x i64> %1, <2 x i64>* @llvm_mips_ftint_s_d_RES
163  ret void
164}
165
166declare <2 x i64> @llvm.mips.ftint.s.d(<2 x double>) nounwind
167
168; CHECK: llvm_mips_ftint_s_d_test:
169; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftint_s_d_ARG1)
170; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
171; CHECK-DAG: ftint_s.d [[WD:\$w[0-9]+]], [[WS]]
172; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftint_s_d_RES)
173; CHECK-DAG: st.d [[WD]], 0([[R2]])
174; CHECK: .size llvm_mips_ftint_s_d_test
175;
176@llvm_mips_ftint_u_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
177@llvm_mips_ftint_u_w_RES  = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
178
179define void @llvm_mips_ftint_u_w_test() nounwind {
180entry:
181  %0 = load <4 x float>, <4 x float>* @llvm_mips_ftint_u_w_ARG1
182  %1 = tail call <4 x i32> @llvm.mips.ftint.u.w(<4 x float> %0)
183  store <4 x i32> %1, <4 x i32>* @llvm_mips_ftint_u_w_RES
184  ret void
185}
186
187declare <4 x i32> @llvm.mips.ftint.u.w(<4 x float>) nounwind
188
189; CHECK: llvm_mips_ftint_u_w_test:
190; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftint_u_w_ARG1)
191; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
192; CHECK-DAG: ftint_u.w [[WD:\$w[0-9]+]], [[WS]]
193; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftint_u_w_RES)
194; CHECK-DAG: st.w [[WD]], 0([[R2]])
195; CHECK: .size llvm_mips_ftint_u_w_test
196;
197@llvm_mips_ftint_u_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
198@llvm_mips_ftint_u_d_RES  = global <2 x i64> <i64 0, i64 0>, align 16
199
200define void @llvm_mips_ftint_u_d_test() nounwind {
201entry:
202  %0 = load <2 x double>, <2 x double>* @llvm_mips_ftint_u_d_ARG1
203  %1 = tail call <2 x i64> @llvm.mips.ftint.u.d(<2 x double> %0)
204  store <2 x i64> %1, <2 x i64>* @llvm_mips_ftint_u_d_RES
205  ret void
206}
207
208declare <2 x i64> @llvm.mips.ftint.u.d(<2 x double>) nounwind
209
210; CHECK: llvm_mips_ftint_u_d_test:
211; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftint_u_d_ARG1)
212; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
213; CHECK-DAG: ftint_u.d [[WD:\$w[0-9]+]], [[WS]]
214; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftint_u_d_RES)
215; CHECK-DAG: st.d [[WD]], 0([[R2]])
216; CHECK: .size llvm_mips_ftint_u_d_test
217;
218