1; Test the MSA intrinsics that are encoded with the I5 instruction format. 2; There are lots of these so this covers those beginning with 'c' 3 4; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 5; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s 6 7@llvm_mips_ceqi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 8@llvm_mips_ceqi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 9 10define void @llvm_mips_ceqi_b_test() nounwind { 11entry: 12 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_ceqi_b_ARG1 13 %1 = tail call <16 x i8> @llvm.mips.ceqi.b(<16 x i8> %0, i32 14) 14 store <16 x i8> %1, <16 x i8>* @llvm_mips_ceqi_b_RES 15 ret void 16} 17 18declare <16 x i8> @llvm.mips.ceqi.b(<16 x i8>, i32) nounwind 19 20; CHECK: llvm_mips_ceqi_b_test: 21; CHECK: ld.b 22; CHECK: ceqi.b 23; CHECK: st.b 24; CHECK: .size llvm_mips_ceqi_b_test 25; 26@llvm_mips_ceqi_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 27@llvm_mips_ceqi_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 28 29define void @llvm_mips_ceqi_h_test() nounwind { 30entry: 31 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_ceqi_h_ARG1 32 %1 = tail call <8 x i16> @llvm.mips.ceqi.h(<8 x i16> %0, i32 14) 33 store <8 x i16> %1, <8 x i16>* @llvm_mips_ceqi_h_RES 34 ret void 35} 36 37declare <8 x i16> @llvm.mips.ceqi.h(<8 x i16>, i32) nounwind 38 39; CHECK: llvm_mips_ceqi_h_test: 40; CHECK: ld.h 41; CHECK: ceqi.h 42; CHECK: st.h 43; CHECK: .size llvm_mips_ceqi_h_test 44; 45@llvm_mips_ceqi_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 46@llvm_mips_ceqi_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 47 48define void @llvm_mips_ceqi_w_test() nounwind { 49entry: 50 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_ceqi_w_ARG1 51 %1 = tail call <4 x i32> @llvm.mips.ceqi.w(<4 x i32> %0, i32 14) 52 store <4 x i32> %1, <4 x i32>* @llvm_mips_ceqi_w_RES 53 ret void 54} 55 56declare <4 x i32> @llvm.mips.ceqi.w(<4 x i32>, i32) nounwind 57 58; CHECK: llvm_mips_ceqi_w_test: 59; CHECK: ld.w 60; CHECK: ceqi.w 61; CHECK: st.w 62; CHECK: .size llvm_mips_ceqi_w_test 63; 64@llvm_mips_ceqi_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 65@llvm_mips_ceqi_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 66 67define void @llvm_mips_ceqi_d_test() nounwind { 68entry: 69 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_ceqi_d_ARG1 70 %1 = tail call <2 x i64> @llvm.mips.ceqi.d(<2 x i64> %0, i32 14) 71 store <2 x i64> %1, <2 x i64>* @llvm_mips_ceqi_d_RES 72 ret void 73} 74 75declare <2 x i64> @llvm.mips.ceqi.d(<2 x i64>, i32) nounwind 76 77; CHECK: llvm_mips_ceqi_d_test: 78; CHECK: ld.d 79; CHECK: ceqi.d 80; CHECK: st.d 81; CHECK: .size llvm_mips_ceqi_d_test 82; 83@llvm_mips_clei_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 84@llvm_mips_clei_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 85 86define void @llvm_mips_clei_s_b_test() nounwind { 87entry: 88 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_clei_s_b_ARG1 89 %1 = tail call <16 x i8> @llvm.mips.clei.s.b(<16 x i8> %0, i32 14) 90 store <16 x i8> %1, <16 x i8>* @llvm_mips_clei_s_b_RES 91 ret void 92} 93 94declare <16 x i8> @llvm.mips.clei.s.b(<16 x i8>, i32) nounwind 95 96; CHECK: llvm_mips_clei_s_b_test: 97; CHECK: ld.b 98; CHECK: clei_s.b 99; CHECK: st.b 100; CHECK: .size llvm_mips_clei_s_b_test 101; 102@llvm_mips_clei_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 103@llvm_mips_clei_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 104 105define void @llvm_mips_clei_s_h_test() nounwind { 106entry: 107 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_clei_s_h_ARG1 108 %1 = tail call <8 x i16> @llvm.mips.clei.s.h(<8 x i16> %0, i32 14) 109 store <8 x i16> %1, <8 x i16>* @llvm_mips_clei_s_h_RES 110 ret void 111} 112 113declare <8 x i16> @llvm.mips.clei.s.h(<8 x i16>, i32) nounwind 114 115; CHECK: llvm_mips_clei_s_h_test: 116; CHECK: ld.h 117; CHECK: clei_s.h 118; CHECK: st.h 119; CHECK: .size llvm_mips_clei_s_h_test 120; 121@llvm_mips_clei_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 122@llvm_mips_clei_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 123 124define void @llvm_mips_clei_s_w_test() nounwind { 125entry: 126 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_clei_s_w_ARG1 127 %1 = tail call <4 x i32> @llvm.mips.clei.s.w(<4 x i32> %0, i32 14) 128 store <4 x i32> %1, <4 x i32>* @llvm_mips_clei_s_w_RES 129 ret void 130} 131 132declare <4 x i32> @llvm.mips.clei.s.w(<4 x i32>, i32) nounwind 133 134; CHECK: llvm_mips_clei_s_w_test: 135; CHECK: ld.w 136; CHECK: clei_s.w 137; CHECK: st.w 138; CHECK: .size llvm_mips_clei_s_w_test 139; 140@llvm_mips_clei_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 141@llvm_mips_clei_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 142 143define void @llvm_mips_clei_s_d_test() nounwind { 144entry: 145 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_clei_s_d_ARG1 146 %1 = tail call <2 x i64> @llvm.mips.clei.s.d(<2 x i64> %0, i32 14) 147 store <2 x i64> %1, <2 x i64>* @llvm_mips_clei_s_d_RES 148 ret void 149} 150 151declare <2 x i64> @llvm.mips.clei.s.d(<2 x i64>, i32) nounwind 152 153; CHECK: llvm_mips_clei_s_d_test: 154; CHECK: ld.d 155; CHECK: clei_s.d 156; CHECK: st.d 157; CHECK: .size llvm_mips_clei_s_d_test 158; 159@llvm_mips_clei_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 160@llvm_mips_clei_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 161 162define void @llvm_mips_clei_u_b_test() nounwind { 163entry: 164 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_clei_u_b_ARG1 165 %1 = tail call <16 x i8> @llvm.mips.clei.u.b(<16 x i8> %0, i32 14) 166 store <16 x i8> %1, <16 x i8>* @llvm_mips_clei_u_b_RES 167 ret void 168} 169 170declare <16 x i8> @llvm.mips.clei.u.b(<16 x i8>, i32) nounwind 171 172; CHECK: llvm_mips_clei_u_b_test: 173; CHECK: ld.b 174; CHECK: clei_u.b 175; CHECK: st.b 176; CHECK: .size llvm_mips_clei_u_b_test 177; 178@llvm_mips_clei_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 179@llvm_mips_clei_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 180 181define void @llvm_mips_clei_u_h_test() nounwind { 182entry: 183 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_clei_u_h_ARG1 184 %1 = tail call <8 x i16> @llvm.mips.clei.u.h(<8 x i16> %0, i32 14) 185 store <8 x i16> %1, <8 x i16>* @llvm_mips_clei_u_h_RES 186 ret void 187} 188 189declare <8 x i16> @llvm.mips.clei.u.h(<8 x i16>, i32) nounwind 190 191; CHECK: llvm_mips_clei_u_h_test: 192; CHECK: ld.h 193; CHECK: clei_u.h 194; CHECK: st.h 195; CHECK: .size llvm_mips_clei_u_h_test 196; 197@llvm_mips_clei_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 198@llvm_mips_clei_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 199 200define void @llvm_mips_clei_u_w_test() nounwind { 201entry: 202 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_clei_u_w_ARG1 203 %1 = tail call <4 x i32> @llvm.mips.clei.u.w(<4 x i32> %0, i32 14) 204 store <4 x i32> %1, <4 x i32>* @llvm_mips_clei_u_w_RES 205 ret void 206} 207 208declare <4 x i32> @llvm.mips.clei.u.w(<4 x i32>, i32) nounwind 209 210; CHECK: llvm_mips_clei_u_w_test: 211; CHECK: ld.w 212; CHECK: clei_u.w 213; CHECK: st.w 214; CHECK: .size llvm_mips_clei_u_w_test 215; 216@llvm_mips_clei_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 217@llvm_mips_clei_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 218 219define void @llvm_mips_clei_u_d_test() nounwind { 220entry: 221 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_clei_u_d_ARG1 222 %1 = tail call <2 x i64> @llvm.mips.clei.u.d(<2 x i64> %0, i32 14) 223 store <2 x i64> %1, <2 x i64>* @llvm_mips_clei_u_d_RES 224 ret void 225} 226 227declare <2 x i64> @llvm.mips.clei.u.d(<2 x i64>, i32) nounwind 228 229; CHECK: llvm_mips_clei_u_d_test: 230; CHECK: ld.d 231; CHECK: clei_u.d 232; CHECK: st.d 233; CHECK: .size llvm_mips_clei_u_d_test 234; 235@llvm_mips_clti_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 236@llvm_mips_clti_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 237 238define void @llvm_mips_clti_s_b_test() nounwind { 239entry: 240 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_clti_s_b_ARG1 241 %1 = tail call <16 x i8> @llvm.mips.clti.s.b(<16 x i8> %0, i32 14) 242 store <16 x i8> %1, <16 x i8>* @llvm_mips_clti_s_b_RES 243 ret void 244} 245 246declare <16 x i8> @llvm.mips.clti.s.b(<16 x i8>, i32) nounwind 247 248; CHECK: llvm_mips_clti_s_b_test: 249; CHECK: ld.b 250; CHECK: clti_s.b 251; CHECK: st.b 252; CHECK: .size llvm_mips_clti_s_b_test 253; 254@llvm_mips_clti_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 255@llvm_mips_clti_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 256 257define void @llvm_mips_clti_s_h_test() nounwind { 258entry: 259 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_clti_s_h_ARG1 260 %1 = tail call <8 x i16> @llvm.mips.clti.s.h(<8 x i16> %0, i32 14) 261 store <8 x i16> %1, <8 x i16>* @llvm_mips_clti_s_h_RES 262 ret void 263} 264 265declare <8 x i16> @llvm.mips.clti.s.h(<8 x i16>, i32) nounwind 266 267; CHECK: llvm_mips_clti_s_h_test: 268; CHECK: ld.h 269; CHECK: clti_s.h 270; CHECK: st.h 271; CHECK: .size llvm_mips_clti_s_h_test 272; 273@llvm_mips_clti_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 274@llvm_mips_clti_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 275 276define void @llvm_mips_clti_s_w_test() nounwind { 277entry: 278 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_clti_s_w_ARG1 279 %1 = tail call <4 x i32> @llvm.mips.clti.s.w(<4 x i32> %0, i32 14) 280 store <4 x i32> %1, <4 x i32>* @llvm_mips_clti_s_w_RES 281 ret void 282} 283 284declare <4 x i32> @llvm.mips.clti.s.w(<4 x i32>, i32) nounwind 285 286; CHECK: llvm_mips_clti_s_w_test: 287; CHECK: ld.w 288; CHECK: clti_s.w 289; CHECK: st.w 290; CHECK: .size llvm_mips_clti_s_w_test 291; 292@llvm_mips_clti_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 293@llvm_mips_clti_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 294 295define void @llvm_mips_clti_s_d_test() nounwind { 296entry: 297 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_clti_s_d_ARG1 298 %1 = tail call <2 x i64> @llvm.mips.clti.s.d(<2 x i64> %0, i32 14) 299 store <2 x i64> %1, <2 x i64>* @llvm_mips_clti_s_d_RES 300 ret void 301} 302 303declare <2 x i64> @llvm.mips.clti.s.d(<2 x i64>, i32) nounwind 304 305; CHECK: llvm_mips_clti_s_d_test: 306; CHECK: ld.d 307; CHECK: clti_s.d 308; CHECK: st.d 309; CHECK: .size llvm_mips_clti_s_d_test 310; 311@llvm_mips_clti_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 312@llvm_mips_clti_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 313 314define void @llvm_mips_clti_u_b_test() nounwind { 315entry: 316 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_clti_u_b_ARG1 317 %1 = tail call <16 x i8> @llvm.mips.clti.u.b(<16 x i8> %0, i32 14) 318 store <16 x i8> %1, <16 x i8>* @llvm_mips_clti_u_b_RES 319 ret void 320} 321 322declare <16 x i8> @llvm.mips.clti.u.b(<16 x i8>, i32) nounwind 323 324; CHECK: llvm_mips_clti_u_b_test: 325; CHECK: ld.b 326; CHECK: clti_u.b 327; CHECK: st.b 328; CHECK: .size llvm_mips_clti_u_b_test 329; 330@llvm_mips_clti_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 331@llvm_mips_clti_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 332 333define void @llvm_mips_clti_u_h_test() nounwind { 334entry: 335 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_clti_u_h_ARG1 336 %1 = tail call <8 x i16> @llvm.mips.clti.u.h(<8 x i16> %0, i32 14) 337 store <8 x i16> %1, <8 x i16>* @llvm_mips_clti_u_h_RES 338 ret void 339} 340 341declare <8 x i16> @llvm.mips.clti.u.h(<8 x i16>, i32) nounwind 342 343; CHECK: llvm_mips_clti_u_h_test: 344; CHECK: ld.h 345; CHECK: clti_u.h 346; CHECK: st.h 347; CHECK: .size llvm_mips_clti_u_h_test 348; 349@llvm_mips_clti_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 350@llvm_mips_clti_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 351 352define void @llvm_mips_clti_u_w_test() nounwind { 353entry: 354 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_clti_u_w_ARG1 355 %1 = tail call <4 x i32> @llvm.mips.clti.u.w(<4 x i32> %0, i32 14) 356 store <4 x i32> %1, <4 x i32>* @llvm_mips_clti_u_w_RES 357 ret void 358} 359 360declare <4 x i32> @llvm.mips.clti.u.w(<4 x i32>, i32) nounwind 361 362; CHECK: llvm_mips_clti_u_w_test: 363; CHECK: ld.w 364; CHECK: clti_u.w 365; CHECK: st.w 366; CHECK: .size llvm_mips_clti_u_w_test 367; 368@llvm_mips_clti_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 369@llvm_mips_clti_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 370 371define void @llvm_mips_clti_u_d_test() nounwind { 372entry: 373 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_clti_u_d_ARG1 374 %1 = tail call <2 x i64> @llvm.mips.clti.u.d(<2 x i64> %0, i32 14) 375 store <2 x i64> %1, <2 x i64>* @llvm_mips_clti_u_d_RES 376 ret void 377} 378 379declare <2 x i64> @llvm.mips.clti.u.d(<2 x i64>, i32) nounwind 380 381; CHECK: llvm_mips_clti_u_d_test: 382; CHECK: ld.d 383; CHECK: clti_u.d 384; CHECK: st.d 385; CHECK: .size llvm_mips_clti_u_d_test 386; 387