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1; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
2
3define void @ashr_v4i32(<4 x i32>* %c) nounwind {
4  ; CHECK-LABEL: ashr_v4i32:
5
6  %1 = ashr <4 x i32> <i32 1, i32 2, i32 4, i32 8>,
7                      <i32 0, i32 1, i32 2, i32 3>
8  ; CHECK-NOT: sra
9  ; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], 1
10  ; CHECK-NOT: sra
11  store volatile <4 x i32> %1, <4 x i32>* %c
12  ; CHECK-DAG: st.w [[R1]], 0($4)
13
14  %2 = ashr <4 x i32> <i32 -2, i32 -4, i32 -8, i32 -16>,
15                      <i32 0, i32 1, i32 2, i32 3>
16  ; CHECK-NOT: sra
17  ; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], -2
18  ; CHECK-NOT: sra
19  store volatile <4 x i32> %2, <4 x i32>* %c
20  ; CHECK-DAG: st.w [[R1]], 0($4)
21
22  ret void
23  ; CHECK-LABEL: .size ashr_v4i32
24}
25
26define void @lshr_v4i32(<4 x i32>* %c) nounwind {
27  ; CHECK-LABEL: lshr_v4i32:
28
29  %1 = lshr <4 x i32> <i32 1, i32 2, i32 4, i32 8>,
30                      <i32 0, i32 1, i32 2, i32 3>
31  ; CHECK-NOT: srl
32  ; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], 1
33  ; CHECK-NOT: srl
34  store volatile <4 x i32> %1, <4 x i32>* %c
35  ; CHECK-DAG: st.w [[R1]], 0($4)
36
37  %2 = lshr <4 x i32> <i32 -2, i32 -4, i32 -8, i32 -16>,
38                      <i32 0, i32 1, i32 2, i32 3>
39  ; CHECK-NOT: srl
40  ; CHECK-DAG: addiu [[CPOOL:\$[0-9]+]], {{.*}}, %lo($
41  ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0([[CPOOL]])
42  ; CHECK-NOT: srl
43  store volatile <4 x i32> %2, <4 x i32>* %c
44  ; CHECK-DAG: st.w [[R1]], 0($4)
45
46  ret void
47  ; CHECK-LABEL: .size lshr_v4i32
48}
49
50define void @shl_v4i32(<4 x i32>* %c) nounwind {
51  ; CHECK-LABEL: shl_v4i32:
52
53  %1 = shl <4 x i32> <i32 8, i32 4, i32 2, i32 1>,
54                     <i32 0, i32 1, i32 2, i32 3>
55  ; CHECK-NOT: sll
56  ; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], 8
57  ; CHECK-NOT: sll
58  store volatile <4 x i32> %1, <4 x i32>* %c
59  ; CHECK-DAG: st.w [[R1]], 0($4)
60
61  %2 = shl <4 x i32> <i32 -8, i32 -4, i32 -2, i32 -1>,
62                     <i32 0, i32 1, i32 2, i32 3>
63  ; CHECK-NOT: sll
64  ; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], -8
65  ; CHECK-NOT: sll
66  store volatile <4 x i32> %2, <4 x i32>* %c
67  ; CHECK-DAG: st.w [[R1]], 0($4)
68
69  ret void
70  ; CHECK-LABEL: .size shl_v4i32
71}
72