1; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck %s 2; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s 3; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 4target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" 5target triple = "powerpc64-unknown-linux-gnu" 6 7define i64 @foo(float %a) nounwind { 8 %x = fptosi float %a to i64 9 ret i64 %x 10 11; CHECK: @foo 12; CHECK: fctidz [[REG:[0-9]+]], 1 13; CHECK: stfd [[REG]], 14; CHECK: ld 3, 15; CHECK: blr 16 17; CHECK-VSX: @foo 18; CHECK-VSX: xscvdpsxds [[REG:[0-9]+]], 1 19; CHECK-VSX: stxsdx [[REG]], 20; CHECK-VSX: ld 3, 21; CHECK-VSX: blr 22} 23 24define i64 @foo2(double %a) nounwind { 25 %x = fptosi double %a to i64 26 ret i64 %x 27 28; CHECK: @foo2 29; CHECK: fctidz [[REG:[0-9]+]], 1 30; CHECK: stfd [[REG]], 31; CHECK: ld 3, 32; CHECK: blr 33 34; CHECK-VSX: @foo2 35; CHECK-VSX: xscvdpsxds [[REG:[0-9]+]], 1 36; CHECK-VSX: stxsdx [[REG]], 37; CHECK-VSX: ld 3, 38; CHECK-VSX: blr 39} 40 41define i64 @foo3(float %a) nounwind { 42 %x = fptoui float %a to i64 43 ret i64 %x 44 45; CHECK: @foo3 46; CHECK: fctiduz [[REG:[0-9]+]], 1 47; CHECK: stfd [[REG]], 48; CHECK: ld 3, 49; CHECK: blr 50 51; CHECK-VSX: @foo3 52; CHECK-VSX: xscvdpuxds [[REG:[0-9]+]], 1 53; CHECK-VSX: stxsdx [[REG]], 54; CHECK-VSX: ld 3, 55; CHECK-VSX: blr 56} 57 58define i64 @foo4(double %a) nounwind { 59 %x = fptoui double %a to i64 60 ret i64 %x 61 62; CHECK: @foo4 63; CHECK: fctiduz [[REG:[0-9]+]], 1 64; CHECK: stfd [[REG]], 65; CHECK: ld 3, 66; CHECK: blr 67 68; CHECK-VSX: @foo4 69; CHECK-VSX: xscvdpuxds [[REG:[0-9]+]], 1 70; CHECK-VSX: stxsdx [[REG]], 71; CHECK-VSX: ld 3, 72; CHECK-VSX: blr 73} 74 75define i32 @goo(float %a) nounwind { 76 %x = fptosi float %a to i32 77 ret i32 %x 78 79; CHECK: @goo 80; CHECK: fctiwz [[REG:[0-9]+]], 1 81; CHECK: stfiwx [[REG]], 82; CHECK: lwz 3, 83; CHECK: blr 84 85; CHECK-VSX: @goo 86; CHECK-VSX: xscvdpsxws [[REG:[0-9]+]], 1 87; CHECK-VSX: stfiwx [[REG]], 88; CHECK-VSX: lwz 3, 89; CHECK-VSX: blr 90} 91 92define i32 @goo2(double %a) nounwind { 93 %x = fptosi double %a to i32 94 ret i32 %x 95 96; CHECK: @goo2 97; CHECK: fctiwz [[REG:[0-9]+]], 1 98; CHECK: stfiwx [[REG]], 99; CHECK: lwz 3, 100; CHECK: blr 101 102; CHECK-VSX: @goo2 103; CHECK-VSX: xscvdpsxws [[REG:[0-9]+]], 1 104; CHECK-VSX: stfiwx [[REG]], 105; CHECK-VSX: lwz 3, 106; CHECK-VSX: blr 107} 108 109define i32 @goo3(float %a) nounwind { 110 %x = fptoui float %a to i32 111 ret i32 %x 112 113; CHECK: @goo3 114; CHECK: fctiwuz [[REG:[0-9]+]], 1 115; CHECK: stfiwx [[REG]], 116; CHECK: lwz 3, 117; CHECK: blr 118 119; CHECK-VSX: @goo3 120; CHECK-VSX: xscvdpuxws [[REG:[0-9]+]], 1 121; CHECK-VSX: stfiwx [[REG]], 122; CHECK-VSX: lwz 3, 123; CHECK-VSX: blr 124} 125 126define i32 @goo4(double %a) nounwind { 127 %x = fptoui double %a to i32 128 ret i32 %x 129 130; CHECK: @goo4 131; CHECK: fctiwuz [[REG:[0-9]+]], 1 132; CHECK: stfiwx [[REG]], 133; CHECK: lwz 3, 134; CHECK: blr 135 136; CHECK-VSX: @goo4 137; CHECK-VSX: xscvdpuxws [[REG:[0-9]+]], 1 138; CHECK-VSX: stfiwx [[REG]], 139; CHECK-VSX: lwz 3, 140; CHECK-VSX: blr 141} 142 143