1; RUN: llc -O3 -mcpu=pwr7 -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-PWR 2; RUN: llc -O3 -mcpu=a2q -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-QPX 3target datalayout = "E-m:e-i64:64-n32:64" 4target triple = "powerpc64-unknown-linux-gnu" 5 6; Verify that the first two adds are independent regardless of how the inputs are 7; commuted. The destination registers are used as source registers for the third add. 8 9define float @reassociate_adds1(float %x0, float %x1, float %x2, float %x3) { 10; CHECK-LABEL: reassociate_adds1: 11; CHECK: # BB#0: 12; CHECK: fadds [[REG0:[0-9]+]], 1, 2 13; CHECK: fadds [[REG1:[0-9]+]], 3, 4 14; CHECK: fadds 1, [[REG0]], [[REG1]] 15; CHECK-NEXT: blr 16 17 %t0 = fadd float %x0, %x1 18 %t1 = fadd float %t0, %x2 19 %t2 = fadd float %t1, %x3 20 ret float %t2 21} 22 23define float @reassociate_adds2(float %x0, float %x1, float %x2, float %x3) { 24; CHECK-LABEL: reassociate_adds2: 25; CHECK: # BB#0: 26; CHECK: fadds [[REG0:[0-9]+]], 1, 2 27; CHECK: fadds [[REG1:[0-9]+]], 3, 4 28; CHECK: fadds 1, [[REG0]], [[REG1]] 29; CHECK-NEXT: blr 30 31 %t0 = fadd float %x0, %x1 32 %t1 = fadd float %x2, %t0 33 %t2 = fadd float %t1, %x3 34 ret float %t2 35} 36 37define float @reassociate_adds3(float %x0, float %x1, float %x2, float %x3) { 38; CHECK-LABEL: reassociate_adds3: 39; CHECK: # BB#0: 40; CHECK: fadds [[REG0:[0-9]+]], 1, 2 41; CHECK: fadds [[REG1:[0-9]+]], 3, 4 42; CHECK: fadds 1, [[REG0]], [[REG1]] 43; CHECK-NEXT: blr 44 45 %t0 = fadd float %x0, %x1 46 %t1 = fadd float %t0, %x2 47 %t2 = fadd float %x3, %t1 48 ret float %t2 49} 50 51define float @reassociate_adds4(float %x0, float %x1, float %x2, float %x3) { 52; CHECK-LABEL: reassociate_adds4: 53; CHECK: # BB#0: 54; CHECK: fadds [[REG0:[0-9]+]], 1, 2 55; CHECK: fadds [[REG1:[0-9]+]], 3, 4 56; CHECK: fadds 1, [[REG0]], [[REG1]] 57; CHECK-NEXT: blr 58 59 %t0 = fadd float %x0, %x1 60 %t1 = fadd float %x2, %t0 61 %t2 = fadd float %x3, %t1 62 ret float %t2 63} 64 65; Verify that we reassociate some of these ops. The optimal balanced tree of adds is not 66; produced because that would cost more compile time. 67 68define float @reassociate_adds5(float %x0, float %x1, float %x2, float %x3, float %x4, float %x5, float %x6, float %x7) { 69; CHECK-LABEL: reassociate_adds5: 70; CHECK: # BB#0: 71; CHECK: fadds [[REG12:[0-9]+]], 5, 6 72; CHECK: fadds [[REG0:[0-9]+]], 1, 2 73; CHECK: fadds [[REG11:[0-9]+]], 3, 4 74; CHECK: fadds [[REG13:[0-9]+]], [[REG12]], 7 75; CHECK: fadds [[REG1:[0-9]+]], [[REG0]], [[REG11]] 76; CHECK: fadds [[REG2:[0-9]+]], [[REG1]], [[REG13]] 77; CHECK: fadds 1, [[REG2]], 8 78; CHECK-NEXT: blr 79 80 %t0 = fadd float %x0, %x1 81 %t1 = fadd float %t0, %x2 82 %t2 = fadd float %t1, %x3 83 %t3 = fadd float %t2, %x4 84 %t4 = fadd float %t3, %x5 85 %t5 = fadd float %t4, %x6 86 %t6 = fadd float %t5, %x7 87 ret float %t6 88} 89 90; Verify that we reassociate vector instructions too. 91 92define <4 x float> @vector_reassociate_adds1(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) { 93; CHECK-LABEL: vector_reassociate_adds1: 94; CHECK: # BB#0: 95; CHECK-QPX: qvfadds [[REG0:[0-9]+]], 1, 2 96; CHECK-QPX: qvfadds [[REG1:[0-9]+]], 3, 4 97; CHECK-QPX: qvfadds 1, [[REG0]], [[REG1]] 98; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35 99; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37 100; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]] 101; CHECK-PWR: # kill 102; CHECK-NEXT: blr 103 104 %t0 = fadd <4 x float> %x0, %x1 105 %t1 = fadd <4 x float> %t0, %x2 106 %t2 = fadd <4 x float> %t1, %x3 107 ret <4 x float> %t2 108} 109 110define <4 x float> @vector_reassociate_adds2(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) { 111; CHECK-LABEL: vector_reassociate_adds2: 112; CHECK: # BB#0: 113; CHECK-QPX: qvfadds [[REG0:[0-9]+]], 1, 2 114; CHECK-QPX: qvfadds [[REG1:[0-9]+]], 3, 4 115; CHECK-QPX: qvfadds 1, [[REG0]], [[REG1]] 116; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35 117; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37 118; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]] 119; CHECK-PWR: # kill 120; CHECK-NEXT: blr 121 122 %t0 = fadd <4 x float> %x0, %x1 123 %t1 = fadd <4 x float> %x2, %t0 124 %t2 = fadd <4 x float> %t1, %x3 125 ret <4 x float> %t2 126} 127 128define <4 x float> @vector_reassociate_adds3(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) { 129; CHECK-LABEL: vector_reassociate_adds3: 130; CHECK: # BB#0: 131; CHECK-QPX: qvfadds [[REG0:[0-9]+]], 1, 2 132; CHECK-QPX: qvfadds [[REG1:[0-9]+]], 3, 4 133; CHECK-QPX: qvfadds 1, [[REG0]], [[REG1]] 134; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35 135; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37 136; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]] 137; CHECK-PWR: # kill 138; CHECK-NEXT: blr 139 140 %t0 = fadd <4 x float> %x0, %x1 141 %t1 = fadd <4 x float> %t0, %x2 142 %t2 = fadd <4 x float> %x3, %t1 143 ret <4 x float> %t2 144} 145 146define <4 x float> @vector_reassociate_adds4(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) { 147; CHECK-LABEL: vector_reassociate_adds4: 148; CHECK: # BB#0: 149; CHECK-QPX: qvfadds [[REG0:[0-9]+]], 1, 2 150; CHECK-QPX: qvfadds [[REG1:[0-9]+]], 3, 4 151; CHECK-QPX: qvfadds 1, [[REG0]], [[REG1]] 152; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35 153; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37 154; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]] 155; CHECK-PWR: # kill 156; CHECK-NEXT: blr 157 158 %t0 = fadd <4 x float> %x0, %x1 159 %t1 = fadd <4 x float> %x2, %t0 160 %t2 = fadd <4 x float> %x3, %t1 161 ret <4 x float> %t2 162} 163 164define float @reassociate_adds6(float %x0, float %x1, float %x2, float %x3) { 165 %t0 = fdiv float %x0, %x1 166 %t1 = fadd float %x2, %t0 167 %t2 = fadd float %x3, %t1 168 ret float %t2 169} 170 171define float @reassociate_muls1(float %x0, float %x1, float %x2, float %x3) { 172 %t0 = fdiv float %x0, %x1 173 %t1 = fmul float %x2, %t0 174 %t2 = fmul float %x3, %t1 175 ret float %t2 176} 177 178define double @reassociate_adds_double(double %x0, double %x1, double %x2, double %x3) { 179 %t0 = fdiv double %x0, %x1 180 %t1 = fadd double %x2, %t0 181 %t2 = fadd double %x3, %t1 182 ret double %t2 183} 184 185define double @reassociate_muls_double(double %x0, double %x1, double %x2, double %x3) { 186 %t0 = fdiv double %x0, %x1 187 %t1 = fmul double %x2, %t0 188 %t2 = fmul double %x3, %t1 189 ret double %t2 190} 191 192 193