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1# RUN: llc -start-after=dead-mi-elimination -stop-after=twoaddressinstruction -o - %s | FileCheck %s
2
3--- |
4  target datalayout = "E-m:e-i64:64-n32:64"
5  target triple = "powerpc64-unknown-linux-gnu"
6
7  @d = global i32 15, align 4
8  @b = global i32* @d, align 8
9  @a = common global i32 0, align 4
10
11  ; Function Attrs: nounwind
12  define signext i32 @main() #0 {
13  entry:
14    %0 = load i32*, i32** @b, align 8
15    %1 = load i32, i32* @a, align 4
16    %lnot = icmp eq i32 %1, 0
17    %lnot.ext = zext i1 %lnot to i32
18    %shr.i = lshr i32 2072, %lnot.ext
19    %call.lobit = lshr i32 %shr.i, 7
20    %2 = and i32 %call.lobit, 1
21    %3 = load i32, i32* %0, align 4
22    %or = or i32 %2, %3
23    store i32 %or, i32* %0, align 4
24    %4 = load i32, i32* @a, align 4
25    %lnot.1 = icmp eq i32 %4, 0
26    %lnot.ext.1 = zext i1 %lnot.1 to i32
27    %shr.i.1 = lshr i32 2072, %lnot.ext.1
28    %call.lobit.1 = lshr i32 %shr.i.1, 7
29    %5 = and i32 %call.lobit.1, 1
30    %or.1 = or i32 %5, %or
31    store i32 %or.1, i32* %0, align 4
32    ret i32 %or.1
33  }
34
35  attributes #0 = { nounwind "target-cpu"="ppc64" }
36
37...
38---
39name:            main
40alignment:       2
41exposesReturnsTwice: false
42hasInlineAsm:    false
43isSSA:           true
44tracksRegLiveness: true
45tracksSubRegLiveness: false
46registers:
47  - { id: 0, class: g8rc_and_g8rc_nox0 }
48  - { id: 1, class: g8rc_and_g8rc_nox0 }
49  - { id: 2, class: gprc }
50  - { id: 3, class: gprc }
51  - { id: 4, class: gprc }
52  - { id: 5, class: g8rc_and_g8rc_nox0 }
53  - { id: 6, class: g8rc_and_g8rc_nox0 }
54  - { id: 7, class: gprc }
55  - { id: 8, class: gprc }
56  - { id: 9, class: gprc }
57  - { id: 10, class: g8rc }
58frameInfo:
59  isFrameAddressTaken: false
60  isReturnAddressTaken: false
61  hasStackMap:     false
62  hasPatchPoint:   false
63  stackSize:       0
64  offsetAdjustment: 0
65  maxAlignment:    0
66  adjustsStack:    false
67  hasCalls:        false
68  maxCallFrameSize: 0
69  hasOpaqueSPAdjustment: false
70  hasVAStart:      false
71  hasMustTailInVarArgFunc: false
72body:             |
73  bb.0.entry:
74    liveins: %x2
75
76    %0 = ADDIStocHA %x2, @b
77    %1 = LD target-flags(ppc-toc-lo) @b, killed %0 :: (load 8 from @b)
78    %2 = LWZ 0, %1 :: (load 4 from %ir.0)
79    %3 = LI 0
80    %4 = RLWIMI %3, killed %2, 0, 0, 31
81    ; CHECK-LABEL: name: main
82    ; CHECK: %[[REG1:[0-9]+]] = LI 0
83    ; CHECK: %[[REG2:[0-9]+]] = COPY %[[REG1]]
84    ; CHECK: %[[REG2]] = RLWIMI %[[REG2]], killed %2, 0, 0, 31
85    %8 = RLWIMI %3, %4, 0, 0, 31
86    STW %4, 0, %1 :: (store 4 into %ir.0)
87    %10 = EXTSW_32_64 %8
88    STW %8, 0, %1 :: (store 4 into %ir.0)
89    %x3 = COPY %10
90    BLR8 implicit %x3, implicit %lr8, implicit %rm
91
92...
93