1; RUN: llc -march=ppc64 -mcpu=pwr7 -O0 -relocation-model=pic < %s | FileCheck -check-prefix=OPT0 %s 2; RUN: llc -march=ppc64 -mcpu=pwr7 -O1 -relocation-model=pic < %s | FileCheck -check-prefix=OPT1 %s 3; RUN: llc -march=ppc32 -O0 -relocation-model=pic < %s | FileCheck -check-prefix=OPT0-32 %s 4; RUN: llc -march=ppc32 -O1 -relocation-model=pic < %s | FileCheck -check-prefix=OPT1-32 %s 5 6target triple = "powerpc64-unknown-linux-gnu" 7; Test correct assembly code generation for thread-local storage using 8; the local dynamic model. 9 10@a = hidden thread_local global i32 0, align 4 11 12define signext i32 @main() nounwind { 13entry: 14 %retval = alloca i32, align 4 15 store i32 0, i32* %retval 16 %0 = load i32, i32* @a, align 4 17 ret i32 %0 18} 19 20; OPT0-LABEL: main: 21; OPT0: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha 22; OPT0: addi 3, [[REG]], a@got@tlsld@l 23; OPT0: bl __tls_get_addr(a@tlsld) 24; OPT0-NEXT: nop 25; OPT0: addis [[REG2:[0-9]+]], 3, a@dtprel@ha 26; OPT0: addi {{[0-9]+}}, [[REG2]], a@dtprel@l 27; OPT0-32-LABEL: main 28; OPT0-32: addi {{[0-9]+}}, {{[0-9]+}}, a@got@tlsld 29; OPT0-32: bl __tls_get_addr(a@tlsld)@PLT 30; OPT0-32: addis [[REG:[0-9]+]], 3, a@dtprel@ha 31; OPT0-32: addi {{[0-9]+}}, [[REG]], a@dtprel@l 32; OPT1-32-LABEL: main 33; OPT1-32: addi 3, {{[0-9]+}}, a@got@tlsld 34; OPT1-32: bl __tls_get_addr(a@tlsld)@PLT 35; OPT1-32: addis [[REG:[0-9]+]], 3, a@dtprel@ha 36; OPT1-32: addi {{[0-9]+}}, [[REG]], a@dtprel@l 37 38; Test peephole optimization for thread-local storage using the 39; local dynamic model. 40 41; OPT1-LABEL: main: 42; OPT1: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha 43; OPT1: addi 3, [[REG]], a@got@tlsld@l 44; OPT1: bl __tls_get_addr(a@tlsld) 45; OPT1-NEXT: nop 46; OPT1: addis [[REG2:[0-9]+]], 3, a@dtprel@ha 47; OPT1: lwa {{[0-9]+}}, a@dtprel@l([[REG2]]) 48 49; Test correct assembly code generation for thread-local storage using 50; the general dynamic model. 51 52@a2 = thread_local global i32 0, align 4 53 54define signext i32 @main2() nounwind { 55entry: 56 %retval = alloca i32, align 4 57 store i32 0, i32* %retval 58 %0 = load i32, i32* @a2, align 4 59 ret i32 %0 60} 61 62; OPT1-LABEL: main2 63; OPT1: addis [[REG:[0-9]+]], 2, a2@got@tlsgd@ha 64; OPT1: addi 3, [[REG]], a2@got@tlsgd@l 65; OPT1: bl __tls_get_addr(a2@tlsgd) 66; OPT1-NEXT: nop 67; OPT1-32-LABEL: main2 68; OPT1-32: addi 3, {{[0-9]+}}, a2@got@tlsgd 69; OPT1-32: bl __tls_get_addr(a2@tlsgd)@PLT 70