1; RUN: llc -march=sparc <%s | FileCheck %s 2 3; CHECK-LABEL: test_constraint_r 4; CHECK: add %o1, %o0, %o0 5define i32 @test_constraint_r(i32 %a, i32 %b) { 6entry: 7 %0 = tail call i32 asm sideeffect "add $2, $1, $0", "=r,r,r"(i32 %a, i32 %b) 8 ret i32 %0 9} 10 11;; Check tests only that the constraints are accepted without a compiler failure. 12; CHECK-LABEL: test_constraints_nro: 13%struct.anon = type { i32, i32 } 14@v = external global %struct.anon, align 4 15define void @test_constraints_nro() { 16entry: 17 %0 = load i32, i32* getelementptr inbounds (%struct.anon, %struct.anon* @v, i32 0, i32 0); 18 %1 = load i32, i32* getelementptr inbounds (%struct.anon, %struct.anon* @v, i32 0, i32 1); 19 tail call void asm sideeffect "", "nro,nro"(i32 %0, i32 %1) 20 ret void 21} 22 23; CHECK-LABEL: test_constraint_I: 24; CHECK: add %o0, 1023, %o0 25define i32 @test_constraint_I(i32 %a) { 26entry: 27 %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 1023) 28 ret i32 %0 29} 30 31; CHECK-LABEL: test_constraint_I_neg: 32; CHECK: add %o0, -4096, %o0 33define i32 @test_constraint_I_neg(i32 %a) { 34entry: 35 %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 -4096) 36 ret i32 %0 37} 38 39; CHECK-LABEL: test_constraint_I_largeimm: 40; CHECK: sethi 9, [[R0:%[gilo][0-7]]] 41; CHECK: or [[R0]], 784, [[R1:%[gilo][0-7]]] 42; CHECK: add %o0, [[R1]], %o0 43define i32 @test_constraint_I_largeimm(i32 %a) { 44entry: 45 %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 10000) 46 ret i32 %0 47} 48 49; CHECK-LABEL: test_constraint_reg: 50; CHECK: ldda [%o1] 43, %g2 51; CHECK: ldda [%o1] 43, %g4 52define void @test_constraint_reg(i32 %s, i32* %ptr) { 53entry: 54 %0 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={r2},r,n"(i32* %ptr, i32 43) 55 %1 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={g4},r,n"(i32* %ptr, i32 43) 56 ret void 57} 58 59;; Ensure that i64 args to asm are allocated to the IntPair register class. 60;; Also checks that register renaming for leaf proc works. 61; CHECK-LABEL: test_constraint_r_i64: 62; CHECK: mov %o0, %o5 63; CHECK: sra %o5, 31, %o4 64; CHECK: std %o4, [%o1] 65define i32 @test_constraint_r_i64(i32 %foo, i64* %out, i32 %o) { 66entry: 67 %conv = sext i32 %foo to i64 68 tail call void asm sideeffect "std $0, [$1]", "r,r,~{memory}"(i64 %conv, i64* %out) 69 ret i32 %o 70} 71 72;; Same test without leaf-proc opt 73; CHECK-LABEL: test_constraint_r_i64_noleaf: 74; CHECK: mov %i0, %i5 75; CHECK: sra %i5, 31, %i4 76; CHECK: std %i4, [%i1] 77define i32 @test_constraint_r_i64_noleaf(i32 %foo, i64* %out, i32 %o) #0 { 78entry: 79 %conv = sext i32 %foo to i64 80 tail call void asm sideeffect "std $0, [$1]", "r,r,~{memory}"(i64 %conv, i64* %out) 81 ret i32 %o 82} 83attributes #0 = { "no-frame-pointer-elim"="true" } 84 85;; Ensures that tied in and out gets allocated properly. 86; CHECK-LABEL: test_i64_inout: 87; CHECK: sethi 0, %o2 88; CHECK: mov 5, %o3 89; CHECK: xor %o2, %g0, %o2 90; CHECK: mov %o2, %o0 91; CHECK: ret 92define i64 @test_i64_inout() { 93entry: 94 %0 = call i64 asm sideeffect "xor $1, %g0, $0", "=r,0,~{i1}"(i64 5); 95 ret i64 %0 96} 97