1; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86-64 -mcpu=corei7 -mattr=avx | FileCheck %s 2; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86-64 -mcpu=corei7 -mattr=avx512vl | FileCheck %s 3 4define i64 @test_x86_sse2_cvtsd2si64(<2 x double> %a0) { 5 ; CHECK: vcvtsd2si 6 %res = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %a0) ; <i64> [#uses=1] 7 ret i64 %res 8} 9declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) nounwind readnone 10 11 12define <2 x double> @test_x86_sse2_cvtsi642sd(<2 x double> %a0, i64 %a1) { 13 ; CHECK: vcvtsi2sd 14 %res = call <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double> %a0, i64 %a1) ; <<2 x double>> [#uses=1] 15 ret <2 x double> %res 16} 17declare <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double>, i64) nounwind readnone 18 19 20define i64 @test_x86_sse2_cvttsd2si64(<2 x double> %a0) { 21 ; CHECK: vcvttsd2si 22 %res = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %a0) ; <i64> [#uses=1] 23 ret i64 %res 24} 25declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind readnone 26 27 28define i64 @test_x86_sse_cvtss2si64(<4 x float> %a0) { 29 ; CHECK: vcvtss2si 30 %res = call i64 @llvm.x86.sse.cvtss2si64(<4 x float> %a0) ; <i64> [#uses=1] 31 ret i64 %res 32} 33declare i64 @llvm.x86.sse.cvtss2si64(<4 x float>) nounwind readnone 34 35 36define <4 x float> @test_x86_sse_cvtsi642ss(<4 x float> %a0, i64 %a1) { 37 ; CHECK: vcvtsi2ss 38 %res = call <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float> %a0, i64 %a1) ; <<4 x float>> [#uses=1] 39 ret <4 x float> %res 40} 41declare <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float>, i64) nounwind readnone 42 43 44define i64 @test_x86_sse_cvttss2si64(<4 x float> %a0) { 45 ; CHECK: vcvttss2si 46 %res = call i64 @llvm.x86.sse.cvttss2si64(<4 x float> %a0) ; <i64> [#uses=1] 47 ret i64 %res 48} 49declare i64 @llvm.x86.sse.cvttss2si64(<4 x float>) nounwind readnone 50 51 52