1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s 3 4define <4 x i32> @trunc4(<4 x i64> %A) nounwind { 5; CHECK-LABEL: trunc4: 6; CHECK: ## BB#0: 7; CHECK-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,0,2,4,6,4,6] 8; CHECK-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,3,2,3] 9; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> 10; CHECK-NEXT: vzeroupper 11; CHECK-NEXT: retq 12 %B = trunc <4 x i64> %A to <4 x i32> 13 ret <4 x i32>%B 14} 15 16define <8 x i16> @trunc8(<8 x i32> %A) nounwind { 17; CHECK-LABEL: trunc8: 18; CHECK: ## BB#0: 19; CHECK-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,20,21,24,25,28,29],zero,zero,zero,zero,zero,zero,zero,zero 20; CHECK-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] 21; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> 22; CHECK-NEXT: vzeroupper 23; CHECK-NEXT: retq 24 %B = trunc <8 x i32> %A to <8 x i16> 25 ret <8 x i16>%B 26} 27 28define <4 x i64> @sext4(<4 x i32> %A) nounwind { 29; CHECK-LABEL: sext4: 30; CHECK: ## BB#0: 31; CHECK-NEXT: vpmovsxdq %xmm0, %ymm0 32; CHECK-NEXT: retq 33 %B = sext <4 x i32> %A to <4 x i64> 34 ret <4 x i64>%B 35} 36 37define <8 x i32> @sext8(<8 x i16> %A) nounwind { 38; CHECK-LABEL: sext8: 39; CHECK: ## BB#0: 40; CHECK-NEXT: vpmovsxwd %xmm0, %ymm0 41; CHECK-NEXT: retq 42 %B = sext <8 x i16> %A to <8 x i32> 43 ret <8 x i32>%B 44} 45 46define <4 x i64> @zext4(<4 x i32> %A) nounwind { 47; CHECK-LABEL: zext4: 48; CHECK: ## BB#0: 49; CHECK-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero 50; CHECK-NEXT: retq 51 %B = zext <4 x i32> %A to <4 x i64> 52 ret <4 x i64>%B 53} 54 55define <8 x i32> @zext8(<8 x i16> %A) nounwind { 56; CHECK-LABEL: zext8: 57; CHECK: ## BB#0: 58; CHECK-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero 59; CHECK-NEXT: retq 60 %B = zext <8 x i16> %A to <8 x i32> 61 ret <8 x i32>%B 62} 63 64define <8 x i32> @zext_8i8_8i32(<8 x i8> %A) nounwind { 65; CHECK-LABEL: zext_8i8_8i32: 66; CHECK: ## BB#0: 67; CHECK-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 68; CHECK-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero 69; CHECK-NEXT: retq 70 %B = zext <8 x i8> %A to <8 x i32> 71 ret <8 x i32>%B 72} 73 74define <16 x i16> @zext_16i8_16i16(<16 x i8> %z) { 75; CHECK-LABEL: zext_16i8_16i16: 76; CHECK: ## BB#0: 77; CHECK-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero 78; CHECK-NEXT: retq 79 %t = zext <16 x i8> %z to <16 x i16> 80 ret <16 x i16> %t 81} 82 83define <16 x i16> @sext_16i8_16i16(<16 x i8> %z) { 84; CHECK-LABEL: sext_16i8_16i16: 85; CHECK: ## BB#0: 86; CHECK-NEXT: vpmovsxbw %xmm0, %ymm0 87; CHECK-NEXT: retq 88 %t = sext <16 x i8> %z to <16 x i16> 89 ret <16 x i16> %t 90} 91 92define <16 x i8> @trunc_16i16_16i8(<16 x i16> %z) { 93; CHECK-LABEL: trunc_16i16_16i8: 94; CHECK: ## BB#0: 95; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm1 96; CHECK-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> 97; CHECK-NEXT: vpshufb %xmm2, %xmm1, %xmm1 98; CHECK-NEXT: vpshufb %xmm2, %xmm0, %xmm0 99; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] 100; CHECK-NEXT: vzeroupper 101; CHECK-NEXT: retq 102 %t = trunc <16 x i16> %z to <16 x i8> 103 ret <16 x i8> %t 104} 105 106define <4 x i64> @load_sext_test1(<4 x i32> *%ptr) { 107; CHECK-LABEL: load_sext_test1: 108; CHECK: ## BB#0: 109; CHECK-NEXT: vpmovsxdq (%rdi), %ymm0 110; CHECK-NEXT: retq 111 %X = load <4 x i32>, <4 x i32>* %ptr 112 %Y = sext <4 x i32> %X to <4 x i64> 113 ret <4 x i64>%Y 114} 115 116define <4 x i64> @load_sext_test2(<4 x i8> *%ptr) { 117; CHECK-LABEL: load_sext_test2: 118; CHECK: ## BB#0: 119; CHECK-NEXT: vpmovsxbq (%rdi), %ymm0 120; CHECK-NEXT: retq 121 %X = load <4 x i8>, <4 x i8>* %ptr 122 %Y = sext <4 x i8> %X to <4 x i64> 123 ret <4 x i64>%Y 124} 125 126define <4 x i64> @load_sext_test3(<4 x i16> *%ptr) { 127; CHECK-LABEL: load_sext_test3: 128; CHECK: ## BB#0: 129; CHECK-NEXT: vpmovsxwq (%rdi), %ymm0 130; CHECK-NEXT: retq 131 %X = load <4 x i16>, <4 x i16>* %ptr 132 %Y = sext <4 x i16> %X to <4 x i64> 133 ret <4 x i64>%Y 134} 135 136define <8 x i32> @load_sext_test4(<8 x i16> *%ptr) { 137; CHECK-LABEL: load_sext_test4: 138; CHECK: ## BB#0: 139; CHECK-NEXT: vpmovsxwd (%rdi), %ymm0 140; CHECK-NEXT: retq 141 %X = load <8 x i16>, <8 x i16>* %ptr 142 %Y = sext <8 x i16> %X to <8 x i32> 143 ret <8 x i32>%Y 144} 145 146define <8 x i32> @load_sext_test5(<8 x i8> *%ptr) { 147; CHECK-LABEL: load_sext_test5: 148; CHECK: ## BB#0: 149; CHECK-NEXT: vpmovsxbd (%rdi), %ymm0 150; CHECK-NEXT: retq 151 %X = load <8 x i8>, <8 x i8>* %ptr 152 %Y = sext <8 x i8> %X to <8 x i32> 153 ret <8 x i32>%Y 154} 155