1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 < %s | FileCheck %s 3; 4; Verify that the DAGCombiner is able to fold a vector AND into a blend 5; if one of the operands to the AND is a vector of all constants, and each 6; constant element is either zero or all-ones. 7 8 9define <4 x i32> @test1(<4 x i32> %A) { 10; CHECK-LABEL: test1: 11; CHECK: # BB#0: 12; CHECK-NEXT: pxor %xmm1, %xmm1 13; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7] 14; CHECK-NEXT: retq 15 %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 0, i32 0> 16 ret <4 x i32> %1 17} 18 19define <4 x i32> @test2(<4 x i32> %A) { 20; CHECK-LABEL: test2: 21; CHECK: # BB#0: 22; CHECK-NEXT: pxor %xmm1, %xmm1 23; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7] 24; CHECK-NEXT: retq 25 %1 = and <4 x i32> %A, <i32 0, i32 -1, i32 0, i32 0> 26 ret <4 x i32> %1 27} 28 29define <4 x i32> @test3(<4 x i32> %A) { 30; CHECK-LABEL: test3: 31; CHECK: # BB#0: 32; CHECK-NEXT: pxor %xmm1, %xmm1 33; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5],xmm1[6,7] 34; CHECK-NEXT: retq 35 %1 = and <4 x i32> %A, <i32 0, i32 0, i32 -1, i32 0> 36 ret <4 x i32> %1 37} 38 39define <4 x i32> @test4(<4 x i32> %A) { 40; CHECK-LABEL: test4: 41; CHECK: # BB#0: 42; CHECK-NEXT: pxor %xmm1, %xmm1 43; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7] 44; CHECK-NEXT: retq 45 %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1> 46 ret <4 x i32> %1 47} 48 49define <4 x i32> @test5(<4 x i32> %A) { 50; CHECK-LABEL: test5: 51; CHECK: # BB#0: 52; CHECK-NEXT: pxor %xmm1, %xmm1 53; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] 54; CHECK-NEXT: retq 55 %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 0> 56 ret <4 x i32> %1 57} 58 59define <4 x i32> @test6(<4 x i32> %A) { 60; CHECK-LABEL: test6: 61; CHECK: # BB#0: 62; CHECK-NEXT: pxor %xmm1, %xmm1 63; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7] 64; CHECK-NEXT: retq 65 %1 = and <4 x i32> %A, <i32 0, i32 -1, i32 0, i32 -1> 66 ret <4 x i32> %1 67} 68 69define <4 x i32> @test7(<4 x i32> %A) { 70; CHECK-LABEL: test7: 71; CHECK: # BB#0: 72; CHECK-NEXT: pxor %xmm1, %xmm1 73; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7] 74; CHECK-NEXT: retq 75 %1 = and <4 x i32> %A, <i32 0, i32 0, i32 -1, i32 -1> 76 ret <4 x i32> %1 77} 78 79define <4 x i32> @test8(<4 x i32> %A) { 80; CHECK-LABEL: test8: 81; CHECK: # BB#0: 82; CHECK-NEXT: pxor %xmm1, %xmm1 83; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5],xmm0[6,7] 84; CHECK-NEXT: retq 85 %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 0, i32 -1> 86 ret <4 x i32> %1 87} 88 89define <4 x i32> @test9(<4 x i32> %A) { 90; CHECK-LABEL: test9: 91; CHECK: # BB#0: 92; CHECK-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero 93; CHECK-NEXT: retq 94 %1 = and <4 x i32> %A, <i32 -1, i32 -1, i32 0, i32 0> 95 ret <4 x i32> %1 96} 97 98define <4 x i32> @test10(<4 x i32> %A) { 99; CHECK-LABEL: test10: 100; CHECK: # BB#0: 101; CHECK-NEXT: pxor %xmm1, %xmm1 102; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7] 103; CHECK-NEXT: retq 104 %1 = and <4 x i32> %A, <i32 0, i32 -1, i32 -1, i32 0> 105 ret <4 x i32> %1 106} 107 108define <4 x i32> @test11(<4 x i32> %A) { 109; CHECK-LABEL: test11: 110; CHECK: # BB#0: 111; CHECK-NEXT: pxor %xmm1, %xmm1 112; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7] 113; CHECK-NEXT: retq 114 %1 = and <4 x i32> %A, <i32 0, i32 -1, i32 -1, i32 -1> 115 ret <4 x i32> %1 116} 117 118define <4 x i32> @test12(<4 x i32> %A) { 119; CHECK-LABEL: test12: 120; CHECK: # BB#0: 121; CHECK-NEXT: pxor %xmm1, %xmm1 122; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7] 123; CHECK-NEXT: retq 124 %1 = and <4 x i32> %A, <i32 -1, i32 -1, i32 -1, i32 0> 125 ret <4 x i32> %1 126} 127 128define <4 x i32> @test13(<4 x i32> %A) { 129; CHECK-LABEL: test13: 130; CHECK: # BB#0: 131; CHECK-NEXT: pxor %xmm1, %xmm1 132; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7] 133; CHECK-NEXT: retq 134 %1 = and <4 x i32> %A, <i32 -1, i32 -1, i32 0, i32 -1> 135 ret <4 x i32> %1 136} 137 138define <4 x i32> @test14(<4 x i32> %A) { 139; CHECK-LABEL: test14: 140; CHECK: # BB#0: 141; CHECK-NEXT: pxor %xmm1, %xmm1 142; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7] 143; CHECK-NEXT: retq 144 %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 -1> 145 ret <4 x i32> %1 146} 147 148define <4 x i32> @test15(<4 x i32> %A, <4 x i32> %B) { 149; CHECK-LABEL: test15: 150; CHECK: # BB#0: 151; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7] 152; CHECK-NEXT: retq 153 %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 -1> 154 %2 = and <4 x i32> %B, <i32 0, i32 -1, i32 0, i32 0> 155 %3 = or <4 x i32> %1, %2 156 ret <4 x i32> %3 157} 158 159define <4 x i32> @test16(<4 x i32> %A, <4 x i32> %B) { 160; CHECK-LABEL: test16: 161; CHECK: # BB#0: 162; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] 163; CHECK-NEXT: retq 164 %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 0> 165 %2 = and <4 x i32> %B, <i32 0, i32 -1, i32 0, i32 -1> 166 %3 = or <4 x i32> %1, %2 167 ret <4 x i32> %3 168} 169 170define <4 x i32> @test17(<4 x i32> %A, <4 x i32> %B) { 171; CHECK-LABEL: test17: 172; CHECK: # BB#0: 173; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7] 174; CHECK-NEXT: retq 175 %1 = and <4 x i32> %A, <i32 0, i32 -1, i32 0, i32 -1> 176 %2 = and <4 x i32> %B, <i32 -1, i32 0, i32 -1, i32 0> 177 %3 = or <4 x i32> %1, %2 178 ret <4 x i32> %3 179} 180