1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse2 < %s | FileCheck %s --check-prefix=SSE2 3; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s --check-prefix=AVX 4 5define <8 x i16> @test1(<8 x i16> %A, <8 x i16> %B) { 6; SSE2-LABEL: test1: 7; SSE2: # BB#0: # %entry 8; SSE2-NEXT: movd %xmm1, %eax 9; SSE2-NEXT: movzwl %ax, %eax 10; SSE2-NEXT: movd %eax, %xmm1 11; SSE2-NEXT: psllw %xmm1, %xmm0 12; SSE2-NEXT: retq 13; 14; AVX-LABEL: test1: 15; AVX: # BB#0: # %entry 16; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 17; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7] 18; AVX-NEXT: vpsllw %xmm1, %xmm0, %xmm0 19; AVX-NEXT: retq 20entry: 21 %vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer 22 %shl = shl <8 x i16> %A, %vecinit14 23 ret <8 x i16> %shl 24} 25 26define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) { 27; SSE2-LABEL: test2: 28; SSE2: # BB#0: # %entry 29; SSE2-NEXT: xorps %xmm2, %xmm2 30; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] 31; SSE2-NEXT: pslld %xmm2, %xmm0 32; SSE2-NEXT: retq 33; 34; AVX-LABEL: test2: 35; AVX: # BB#0: # %entry 36; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 37; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7] 38; AVX-NEXT: vpslld %xmm1, %xmm0, %xmm0 39; AVX-NEXT: retq 40entry: 41 %vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer 42 %shl = shl <4 x i32> %A, %vecinit6 43 ret <4 x i32> %shl 44} 45 46define <2 x i64> @test3(<2 x i64> %A, <2 x i64> %B) { 47; SSE2-LABEL: test3: 48; SSE2: # BB#0: # %entry 49; SSE2-NEXT: psllq %xmm1, %xmm0 50; SSE2-NEXT: retq 51; 52; AVX-LABEL: test3: 53; AVX: # BB#0: # %entry 54; AVX-NEXT: vpsllq %xmm1, %xmm0, %xmm0 55; AVX-NEXT: retq 56entry: 57 %vecinit2 = shufflevector <2 x i64> %B, <2 x i64> undef, <2 x i32> zeroinitializer 58 %shl = shl <2 x i64> %A, %vecinit2 59 ret <2 x i64> %shl 60} 61 62define <8 x i16> @test4(<8 x i16> %A, <8 x i16> %B) { 63; SSE2-LABEL: test4: 64; SSE2: # BB#0: # %entry 65; SSE2-NEXT: movd %xmm1, %eax 66; SSE2-NEXT: movzwl %ax, %eax 67; SSE2-NEXT: movd %eax, %xmm1 68; SSE2-NEXT: psrlw %xmm1, %xmm0 69; SSE2-NEXT: retq 70; 71; AVX-LABEL: test4: 72; AVX: # BB#0: # %entry 73; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 74; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7] 75; AVX-NEXT: vpsrlw %xmm1, %xmm0, %xmm0 76; AVX-NEXT: retq 77entry: 78 %vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer 79 %shr = lshr <8 x i16> %A, %vecinit14 80 ret <8 x i16> %shr 81} 82 83define <4 x i32> @test5(<4 x i32> %A, <4 x i32> %B) { 84; SSE2-LABEL: test5: 85; SSE2: # BB#0: # %entry 86; SSE2-NEXT: xorps %xmm2, %xmm2 87; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] 88; SSE2-NEXT: psrld %xmm2, %xmm0 89; SSE2-NEXT: retq 90; 91; AVX-LABEL: test5: 92; AVX: # BB#0: # %entry 93; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 94; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7] 95; AVX-NEXT: vpsrld %xmm1, %xmm0, %xmm0 96; AVX-NEXT: retq 97entry: 98 %vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer 99 %shr = lshr <4 x i32> %A, %vecinit6 100 ret <4 x i32> %shr 101} 102 103define <2 x i64> @test6(<2 x i64> %A, <2 x i64> %B) { 104; SSE2-LABEL: test6: 105; SSE2: # BB#0: # %entry 106; SSE2-NEXT: psrlq %xmm1, %xmm0 107; SSE2-NEXT: retq 108; 109; AVX-LABEL: test6: 110; AVX: # BB#0: # %entry 111; AVX-NEXT: vpsrlq %xmm1, %xmm0, %xmm0 112; AVX-NEXT: retq 113entry: 114 %vecinit2 = shufflevector <2 x i64> %B, <2 x i64> undef, <2 x i32> zeroinitializer 115 %shr = lshr <2 x i64> %A, %vecinit2 116 ret <2 x i64> %shr 117} 118 119define <8 x i16> @test7(<8 x i16> %A, <8 x i16> %B) { 120; SSE2-LABEL: test7: 121; SSE2: # BB#0: # %entry 122; SSE2-NEXT: movd %xmm1, %eax 123; SSE2-NEXT: movzwl %ax, %eax 124; SSE2-NEXT: movd %eax, %xmm1 125; SSE2-NEXT: psraw %xmm1, %xmm0 126; SSE2-NEXT: retq 127; 128; AVX-LABEL: test7: 129; AVX: # BB#0: # %entry 130; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 131; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7] 132; AVX-NEXT: vpsraw %xmm1, %xmm0, %xmm0 133; AVX-NEXT: retq 134entry: 135 %vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer 136 %shr = ashr <8 x i16> %A, %vecinit14 137 ret <8 x i16> %shr 138} 139 140define <4 x i32> @test8(<4 x i32> %A, <4 x i32> %B) { 141; SSE2-LABEL: test8: 142; SSE2: # BB#0: # %entry 143; SSE2-NEXT: xorps %xmm2, %xmm2 144; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] 145; SSE2-NEXT: psrad %xmm2, %xmm0 146; SSE2-NEXT: retq 147; 148; AVX-LABEL: test8: 149; AVX: # BB#0: # %entry 150; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 151; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7] 152; AVX-NEXT: vpsrad %xmm1, %xmm0, %xmm0 153; AVX-NEXT: retq 154entry: 155 %vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer 156 %shr = ashr <4 x i32> %A, %vecinit6 157 ret <4 x i32> %shr 158} 159