1; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse4.1,-avx < %s | FileCheck %s --check-prefix SSE41 2; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx,-avx2 < %s | FileCheck %s --check-prefix AVX 3 4define i32 @veccond128(<4 x i32> %input) { 5entry: 6 %0 = bitcast <4 x i32> %input to i128 7 %1 = icmp ne i128 %0, 0 8 br i1 %1, label %if-true-block, label %endif-block 9 10if-true-block: ; preds = %entry 11 ret i32 0 12endif-block: ; preds = %entry, 13 ret i32 1 14; SSE41: veccond128 15; SSE41: ptest 16; SSE41: ret 17; AVX: veccond128 18; AVX: vptest %xmm{{.*}}, %xmm{{.*}} 19; AVX: ret 20} 21 22define i32 @veccond256(<8 x i32> %input) { 23entry: 24 %0 = bitcast <8 x i32> %input to i256 25 %1 = icmp ne i256 %0, 0 26 br i1 %1, label %if-true-block, label %endif-block 27 28if-true-block: ; preds = %entry 29 ret i32 0 30endif-block: ; preds = %entry, 31 ret i32 1 32; SSE41: veccond256 33; SSE41: por 34; SSE41: ptest 35; SSE41: ret 36; AVX: veccond256 37; AVX: vptest %ymm{{.*}}, %ymm{{.*}} 38; AVX: ret 39} 40 41define i32 @veccond512(<16 x i32> %input) { 42entry: 43 %0 = bitcast <16 x i32> %input to i512 44 %1 = icmp ne i512 %0, 0 45 br i1 %1, label %if-true-block, label %endif-block 46 47if-true-block: ; preds = %entry 48 ret i32 0 49endif-block: ; preds = %entry, 50 ret i32 1 51; SSE41: veccond512 52; SSE41: por 53; SSE41: por 54; SSE41: por 55; SSE41: ptest 56; SSE41: ret 57; AVX: veccond512 58; AVX: vorps 59; AVX: vptest %ymm{{.*}}, %ymm{{.*}} 60; AVX: ret 61} 62 63define i32 @vectest128(<4 x i32> %input) { 64entry: 65 %0 = bitcast <4 x i32> %input to i128 66 %1 = icmp ne i128 %0, 0 67 %2 = zext i1 %1 to i32 68 ret i32 %2 69; SSE41: vectest128 70; SSE41: ptest 71; SSE41: ret 72; AVX: vectest128 73; AVX: vptest %xmm{{.*}}, %xmm{{.*}} 74; AVX: ret 75} 76 77define i32 @vectest256(<8 x i32> %input) { 78entry: 79 %0 = bitcast <8 x i32> %input to i256 80 %1 = icmp ne i256 %0, 0 81 %2 = zext i1 %1 to i32 82 ret i32 %2 83; SSE41: vectest256 84; SSE41: por 85; SSE41: ptest 86; SSE41: ret 87; AVX: vectest256 88; AVX: vptest %ymm{{.*}}, %ymm{{.*}} 89; AVX: ret 90} 91 92define i32 @vectest512(<16 x i32> %input) { 93entry: 94 %0 = bitcast <16 x i32> %input to i512 95 %1 = icmp ne i512 %0, 0 96 %2 = zext i1 %1 to i32 97 ret i32 %2 98; SSE41: vectest512 99; SSE41: por 100; SSE41: por 101; SSE41: por 102; SSE41: ptest 103; SSE41: ret 104; AVX: vectest512 105; AVX: vorps 106; AVX: vptest %ymm{{.*}}, %ymm{{.*}} 107; AVX: ret 108} 109 110define i32 @vecsel128(<4 x i32> %input, i32 %a, i32 %b) { 111entry: 112 %0 = bitcast <4 x i32> %input to i128 113 %1 = icmp ne i128 %0, 0 114 %2 = select i1 %1, i32 %a, i32 %b 115 ret i32 %2 116; SSE41: vecsel128 117; SSE41: ptest 118; SSE41: ret 119; AVX: vecsel128 120; AVX: vptest %xmm{{.*}}, %xmm{{.*}} 121; AVX: ret 122} 123 124define i32 @vecsel256(<8 x i32> %input, i32 %a, i32 %b) { 125entry: 126 %0 = bitcast <8 x i32> %input to i256 127 %1 = icmp ne i256 %0, 0 128 %2 = select i1 %1, i32 %a, i32 %b 129 ret i32 %2 130; SSE41: vecsel256 131; SSE41: por 132; SSE41: ptest 133; SSE41: ret 134; AVX: vecsel256 135; AVX: vptest %ymm{{.*}}, %ymm{{.*}} 136; AVX: ret 137} 138 139define i32 @vecsel512(<16 x i32> %input, i32 %a, i32 %b) { 140entry: 141 %0 = bitcast <16 x i32> %input to i512 142 %1 = icmp ne i512 %0, 0 143 %2 = select i1 %1, i32 %a, i32 %b 144 ret i32 %2 145; SSE41: vecsel512 146; SSE41: por 147; SSE41: por 148; SSE41: por 149; SSE41: ptest 150; SSE41: ret 151; AVX: vecsel512 152; AVX: vorps 153; AVX: vptest %ymm{{.*}}, %ymm{{.*}} 154; AVX: ret 155} 156