1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s 3 4target triple = "x86_64-unknown-unknown" 5 6; widening shuffle v3float and then a add 7define void @shuf(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind { 8; CHECK-LABEL: shuf: 9; CHECK: # BB#0: # %entry 10; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 11; CHECK-NEXT: addps %xmm1, %xmm0 12; CHECK-NEXT: extractps $2, %xmm0, 8(%eax) 13; CHECK-NEXT: extractps $1, %xmm0, 4(%eax) 14; CHECK-NEXT: movss %xmm0, (%eax) 15; CHECK-NEXT: retl 16entry: 17 %x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 1, i32 2> 18 %val = fadd <3 x float> %x, %src2 19 store <3 x float> %val, <3 x float>* %dst.addr 20 ret void 21} 22 23 24; widening shuffle v3float with a different mask and then a add 25define void @shuf2(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind { 26; CHECK-LABEL: shuf2: 27; CHECK: # BB#0: # %entry 28; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 29; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3] 30; CHECK-NEXT: addps %xmm1, %xmm0 31; CHECK-NEXT: extractps $2, %xmm0, 8(%eax) 32; CHECK-NEXT: extractps $1, %xmm0, 4(%eax) 33; CHECK-NEXT: movss %xmm0, (%eax) 34; CHECK-NEXT: retl 35entry: 36 %x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 4, i32 2> 37 %val = fadd <3 x float> %x, %src2 38 store <3 x float> %val, <3 x float>* %dst.addr 39 ret void 40} 41 42; Example of when widening a v3float operation causes the DAG to replace a node 43; with the operation that we are currently widening, i.e. when replacing 44; opA with opB, the DAG will produce new operations with opA. 45define void @shuf3(<4 x float> %tmp10, <4 x float> %vecinit15, <4 x float>* %dst) nounwind { 46; CHECK-LABEL: shuf3: 47; CHECK: # BB#0: # %entry 48; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 49; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0] 50; CHECK-NEXT: movaps %xmm1, (%eax) 51; CHECK-NEXT: retl 52entry: 53 %shuffle.i.i.i12 = shufflevector <4 x float> %tmp10, <4 x float> %vecinit15, <4 x i32> <i32 0, i32 1, i32 4, i32 5> 54 %tmp25.i.i = shufflevector <4 x float> %shuffle.i.i.i12, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2> 55 %tmp1.i.i = shufflevector <3 x float> %tmp25.i.i, <3 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 56 %tmp3.i13 = shufflevector <4 x float> %tmp1.i.i, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2> ; <<3 x float>> 57 %tmp6.i14 = shufflevector <3 x float> %tmp3.i13, <3 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 58 %tmp97.i = shufflevector <4 x float> %tmp6.i14, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2> 59 %tmp2.i18 = shufflevector <3 x float> %tmp97.i, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2> 60 %t5 = bitcast <4 x float> %tmp2.i18 to <4 x i32> 61 %shr.i.i19 = lshr <4 x i32> %t5, <i32 19, i32 19, i32 19, i32 19> 62 %and.i.i20 = and <4 x i32> %shr.i.i19, <i32 4080, i32 4080, i32 4080, i32 4080> 63 %shuffle.i.i.i21 = shufflevector <4 x float> %tmp2.i18, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3> 64 store <4 x float> %shuffle.i.i.i21, <4 x float>* %dst 65 ret void 66} 67 68; PR10421: make sure we correctly handle extreme widening with CONCAT_VECTORS 69define <8 x i8> @shuf4(<4 x i8> %a, <4 x i8> %b) nounwind readnone { 70; CHECK-LABEL: shuf4: 71; CHECK: # BB#0: 72; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] 73; CHECK-NEXT: pshufb %xmm2, %xmm1 74; CHECK-NEXT: pshufb %xmm2, %xmm0 75; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] 76; CHECK-NEXT: retl 77 %vshuf = shufflevector <4 x i8> %a, <4 x i8> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 78 ret <8 x i8> %vshuf 79} 80 81; PR11389: another CONCAT_VECTORS case 82define void @shuf5(<8 x i8>* %p) nounwind { 83; CHECK-LABEL: shuf5: 84; CHECK: # BB#0: 85; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 86; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [33,33,33,33,33,33,33,33] 87; CHECK-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] 88; CHECK-NEXT: movq %xmm0, (%eax) 89; CHECK-NEXT: retl 90 %v = shufflevector <2 x i8> <i8 4, i8 33>, <2 x i8> undef, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 91 store <8 x i8> %v, <8 x i8>* %p, align 8 92 ret void 93} 94