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1// RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s
2
3// Check that the assembler can handle the documented syntax for AArch64
4
5//------------------------------------------------------------------------------
6// Load multiple 1-element structures from one register (post-index)
7//------------------------------------------------------------------------------
8         ld1 { v0.16b }, [x0], x1
9         ld1 { v15.8h }, [x15], x2
10         ld1 { v31.4s }, [sp], #16
11         ld1 { v0.2d }, [x0], #16
12         ld1 { v0.8b }, [x0], x2
13         ld1 { v15.4h }, [x15], x3
14         ld1 { v31.2s }, [sp], #8
15         ld1 { v0.1d }, [x0], #8
16// CHECK: ld1 { v0.16b }, [x0], x1
17// CHECK:     // encoding: [0x00,0x70,0xc1,0x4c]
18// CHECK: ld1 { v15.8h }, [x15], x2
19// CHECK:     // encoding: [0xef,0x75,0xc2,0x4c]
20// CHECK: ld1 { v31.4s }, [sp], #16
21// CHECK:     // encoding: [0xff,0x7b,0xdf,0x4c]
22// CHECK: ld1 { v0.2d }, [x0], #16
23// CHECK:     // encoding: [0x00,0x7c,0xdf,0x4c]
24// CHECK: ld1 { v0.8b }, [x0], x2
25// CHECK:     // encoding: [0x00,0x70,0xc2,0x0c]
26// CHECK: ld1 { v15.4h }, [x15], x3
27// CHECK:     // encoding: [0xef,0x75,0xc3,0x0c]
28// CHECK: ld1 { v31.2s }, [sp], #8
29// CHECK:     // encoding: [0xff,0x7b,0xdf,0x0c]
30// CHECK: ld1 { v0.1d }, [x0], #8
31// CHECK:     // encoding: [0x00,0x7c,0xdf,0x0c]
32
33//------------------------------------------------------------------------------
34// Load multiple 1-element structures from two consecutive registers
35// (post-index)
36//------------------------------------------------------------------------------
37         ld1 { v0.16b, v1.16b }, [x0], x1
38         ld1 { v15.8h, v16.8h }, [x15], x2
39         ld1 { v31.4s, v0.4s }, [sp], #32
40         ld1 { v0.2d, v1.2d }, [x0], #32
41         ld1 { v0.8b, v1.8b }, [x0], x2
42         ld1 { v15.4h, v16.4h }, [x15], x3
43         ld1 { v31.2s, v0.2s }, [sp], #16
44         ld1 { v0.1d, v1.1d }, [x0], #16
45// CHECK: ld1 { v0.16b, v1.16b }, [x0], x1
46// CHECK:     // encoding: [0x00,0xa0,0xc1,0x4c]
47// CHECK: ld1 { v15.8h, v16.8h }, [x15], x2
48// CHECK:     // encoding: [0xef,0xa5,0xc2,0x4c]
49// CHECK: ld1 { v31.4s, v0.4s }, [sp], #32
50// CHECK:     // encoding: [0xff,0xab,0xdf,0x4c]
51// CHECK: ld1 { v0.2d, v1.2d }, [x0], #32
52// CHECK:     // encoding: [0x00,0xac,0xdf,0x4c]
53// CHECK: ld1 { v0.8b, v1.8b }, [x0], x2
54// CHECK:     // encoding: [0x00,0xa0,0xc2,0x0c]
55// CHECK: ld1 { v15.4h, v16.4h }, [x15], x3
56// CHECK:     // encoding: [0xef,0xa5,0xc3,0x0c]
57// CHECK: ld1 { v31.2s, v0.2s }, [sp], #16
58// CHECK:     // encoding: [0xff,0xab,0xdf,0x0c]
59// CHECK: ld1 { v0.1d, v1.1d }, [x0], #16
60// CHECK:     // encoding: [0x00,0xac,0xdf,0x0c]
61
62//------------------------------------------------------------------------------
63// Load multiple 1-element structures from three consecutive registers
64// (post-index)
65//------------------------------------------------------------------------------
66         ld1 { v0.16b, v1.16b, v2.16b }, [x0], x1
67         ld1 { v15.8h, v16.8h, v17.8h }, [x15], x2
68         ld1 { v31.4s, v0.4s, v1.4s }, [sp], #48
69         ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48
70         ld1 { v0.8b, v1.8b, v2.8b }, [x0], x2
71         ld1 { v15.4h, v16.4h, v17.4h }, [x15], x3
72         ld1 { v31.2s, v0.2s, v1.2s }, [sp], #24
73         ld1 { v0.1d, v1.1d, v2.1d }, [x0], #24
74// CHECK: ld1 { v0.16b, v1.16b, v2.16b }, [x0], x1
75// CHECK:     // encoding: [0x00,0x60,0xc1,0x4c]
76// CHECK: ld1 { v15.8h, v16.8h, v17.8h }, [x15], x2
77// CHECK:     // encoding: [0xef,0x65,0xc2,0x4c]
78// CHECK: ld1 { v31.4s, v0.4s, v1.4s }, [sp], #48
79// CHECK:     // encoding: [0xff,0x6b,0xdf,0x4c]
80// CHECK: ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48
81// CHECK:     // encoding: [0x00,0x6c,0xdf,0x4c]
82// CHECK: ld1 { v0.8b, v1.8b, v2.8b }, [x0], x2
83// CHECK:     // encoding: [0x00,0x60,0xc2,0x0c]
84// CHECK: ld1 { v15.4h, v16.4h, v17.4h }, [x15], x3
85// CHECK:     // encoding: [0xef,0x65,0xc3,0x0c]
86// CHECK: ld1 { v31.2s, v0.2s, v1.2s }, [sp], #24
87// CHECK:     // encoding: [0xff,0x6b,0xdf,0x0c]
88// CHECK: ld1 { v0.1d, v1.1d, v2.1d }, [x0], #24
89// CHECK:     // encoding: [0x00,0x6c,0xdf,0x0c]
90
91//------------------------------------------------------------------------------
92// Load multiple 1-element structures from four consecutive registers
93// (post-index)
94//------------------------------------------------------------------------------
95         ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1
96         ld1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2
97         ld1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64
98         ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64
99         ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
100         ld1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4
101         ld1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32
102         ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0], #32
103// CHECK: ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1
104// CHECK:     // encoding: [0x00,0x20,0xc1,0x4c]
105// CHECK: ld1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2
106// CHECK:     // encoding: [0xef,0x25,0xc2,0x4c]
107// CHECK: ld1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64
108// CHECK:     // encoding: [0xff,0x2b,0xdf,0x4c]
109// CHECK: ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64
110// CHECK:     // encoding: [0x00,0x2c,0xdf,0x4c]
111// CHECK: ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
112// CHECK:     // encoding: [0x00,0x20,0xc3,0x0c]
113// CHECK: ld1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4
114// CHECK:     // encoding: [0xef,0x25,0xc4,0x0c]
115// CHECK: ld1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32
116// CHECK:     // encoding: [0xff,0x2b,0xdf,0x0c]
117// CHECK: ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0], #32
118// CHECK:     // encoding: [0x00,0x2c,0xdf,0x0c]
119
120//------------------------------------------------------------------------------
121// Load multiple 2-element structures from two consecutive registers
122// (post-index)
123//------------------------------------------------------------------------------
124         ld2 { v0.16b, v1.16b }, [x0], x1
125         ld2 { v15.8h, v16.8h }, [x15], x2
126         ld2 { v31.4s, v0.4s }, [sp], #32
127         ld2 { v0.2d, v1.2d }, [x0], #32
128         ld2 { v0.8b, v1.8b }, [x0], x2
129         ld2 { v15.4h, v16.4h }, [x15], x3
130         ld2 { v31.2s, v0.2s }, [sp], #16
131// CHECK: ld2 { v0.16b, v1.16b }, [x0], x1
132// CHECK:     // encoding: [0x00,0x80,0xc1,0x4c]
133// CHECK: ld2 { v15.8h, v16.8h }, [x15], x2
134// CHECK:     // encoding: [0xef,0x85,0xc2,0x4c]
135// CHECK: ld2 { v31.4s, v0.4s }, [sp], #32
136// CHECK:     // encoding: [0xff,0x8b,0xdf,0x4c]
137// CHECK: ld2 { v0.2d, v1.2d }, [x0], #32
138// CHECK:     // encoding: [0x00,0x8c,0xdf,0x4c]
139// CHECK: ld2 { v0.8b, v1.8b }, [x0], x2
140// CHECK:     // encoding: [0x00,0x80,0xc2,0x0c]
141// CHECK: ld2 { v15.4h, v16.4h }, [x15], x3
142// CHECK:     // encoding: [0xef,0x85,0xc3,0x0c]
143// CHECK: ld2 { v31.2s, v0.2s }, [sp], #16
144// CHECK:     // encoding: [0xff,0x8b,0xdf,0x0c]
145
146//------------------------------------------------------------------------------
147// Load multiple 3-element structures from three consecutive registers
148// (post-index)
149//------------------------------------------------------------------------------
150         ld3 { v0.16b, v1.16b, v2.16b }, [x0], x1
151         ld3 { v15.8h, v16.8h, v17.8h }, [x15], x2
152         ld3 { v31.4s, v0.4s, v1.4s }, [sp], #48
153         ld3 { v0.2d, v1.2d, v2.2d }, [x0], #48
154         ld3 { v0.8b, v1.8b, v2.8b }, [x0], x2
155         ld3 { v15.4h, v16.4h, v17.4h }, [x15], x3
156         ld3 { v31.2s, v0.2s, v1.2s }, [sp], #24
157// CHECK: ld3 { v0.16b, v1.16b, v2.16b }, [x0], x1
158// CHECK:     // encoding: [0x00,0x40,0xc1,0x4c]
159// CHECK: ld3 { v15.8h, v16.8h, v17.8h }, [x15], x2
160// CHECK:     // encoding: [0xef,0x45,0xc2,0x4c]
161// CHECK: ld3 { v31.4s, v0.4s, v1.4s }, [sp], #48
162// CHECK:     // encoding: [0xff,0x4b,0xdf,0x4c]
163// CHECK: ld3 { v0.2d, v1.2d, v2.2d }, [x0], #48
164// CHECK:     // encoding: [0x00,0x4c,0xdf,0x4c]
165// CHECK: ld3 { v0.8b, v1.8b, v2.8b }, [x0], x2
166// CHECK:     // encoding: [0x00,0x40,0xc2,0x0c]
167// CHECK: ld3 { v15.4h, v16.4h, v17.4h }, [x15], x3
168// CHECK:     // encoding: [0xef,0x45,0xc3,0x0c]
169// CHECK: ld3 { v31.2s, v0.2s, v1.2s }, [sp], #24
170// CHECK:     // encoding: [0xff,0x4b,0xdf,0x0c]
171
172//------------------------------------------------------------------------------
173// Load multiple 4-element structures from four consecutive registers
174// (post-index)
175//------------------------------------------------------------------------------
176         ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1
177         ld4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2
178         ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64
179         ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64
180         ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
181         ld4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4
182         ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32
183// CHECK: ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1
184// CHECK:     // encoding: [0x00,0x00,0xc1,0x4c]
185// CHECK: ld4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2
186// CHECK:     // encoding: [0xef,0x05,0xc2,0x4c]
187// CHECK: ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64
188// CHECK:     // encoding: [0xff,0x0b,0xdf,0x4c]
189// CHECK: ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64
190// CHECK:     // encoding: [0x00,0x0c,0xdf,0x4c]
191// CHECK: ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
192// CHECK:     // encoding: [0x00,0x00,0xc3,0x0c]
193// CHECK: ld4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4
194// CHECK:     // encoding: [0xef,0x05,0xc4,0x0c]
195// CHECK: ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32
196// CHECK:     // encoding: [0xff,0x0b,0xdf,0x0c]
197
198//------------------------------------------------------------------------------
199// Store multiple 1-element structures from one register (post-index)
200//------------------------------------------------------------------------------
201         st1 { v0.16b }, [x0], x1
202         st1 { v15.8h }, [x15], x2
203         st1 { v31.4s }, [sp], #16
204         st1 { v0.2d }, [x0], #16
205         st1 { v0.8b }, [x0], x2
206         st1 { v15.4h }, [x15], x3
207         st1 { v31.2s }, [sp], #8
208         st1 { v0.1d }, [x0], #8
209// CHECK: st1 { v0.16b }, [x0], x1
210// CHECK:     // encoding: [0x00,0x70,0x81,0x4c]
211// CHECK: st1 { v15.8h }, [x15], x2
212// CHECK:     // encoding: [0xef,0x75,0x82,0x4c]
213// CHECK: st1 { v31.4s }, [sp], #16
214// CHECK:     // encoding: [0xff,0x7b,0x9f,0x4c]
215// CHECK: st1 { v0.2d }, [x0], #16
216// CHECK:     // encoding: [0x00,0x7c,0x9f,0x4c]
217// CHECK: st1 { v0.8b }, [x0], x2
218// CHECK:     // encoding: [0x00,0x70,0x82,0x0c]
219// CHECK: st1 { v15.4h }, [x15], x3
220// CHECK:     // encoding: [0xef,0x75,0x83,0x0c]
221// CHECK: st1 { v31.2s }, [sp], #8
222// CHECK:     // encoding: [0xff,0x7b,0x9f,0x0c]
223// CHECK: st1 { v0.1d }, [x0], #8
224// CHECK:     // encoding: [0x00,0x7c,0x9f,0x0c]
225
226//------------------------------------------------------------------------------
227// Store multiple 1-element structures from two consecutive registers
228// (post-index)
229//------------------------------------------------------------------------------
230         st1 { v0.16b, v1.16b }, [x0], x1
231         st1 { v15.8h, v16.8h }, [x15], x2
232         st1 { v31.4s, v0.4s }, [sp], #32
233         st1 { v0.2d, v1.2d }, [x0], #32
234         st1 { v0.8b, v1.8b }, [x0], x2
235         st1 { v15.4h, v16.4h }, [x15], x3
236         st1 { v31.2s, v0.2s }, [sp], #16
237         st1 { v0.1d, v1.1d }, [x0], #16
238// CHECK: st1 { v0.16b, v1.16b }, [x0], x1
239// CHECK:     // encoding: [0x00,0xa0,0x81,0x4c]
240// CHECK: st1 { v15.8h, v16.8h }, [x15], x2
241// CHECK:     // encoding: [0xef,0xa5,0x82,0x4c]
242// CHECK: st1 { v31.4s, v0.4s }, [sp], #32
243// CHECK:     // encoding: [0xff,0xab,0x9f,0x4c]
244// CHECK: st1 { v0.2d, v1.2d }, [x0], #32
245// CHECK:     // encoding: [0x00,0xac,0x9f,0x4c]
246// CHECK: st1 { v0.8b, v1.8b }, [x0], x2
247// CHECK:     // encoding: [0x00,0xa0,0x82,0x0c]
248// CHECK: st1 { v15.4h, v16.4h }, [x15], x3
249// CHECK:     // encoding: [0xef,0xa5,0x83,0x0c]
250// CHECK: st1 { v31.2s, v0.2s }, [sp], #16
251// CHECK:     // encoding: [0xff,0xab,0x9f,0x0c]
252// CHECK: st1 { v0.1d, v1.1d }, [x0], #16
253// CHECK:     // encoding: [0x00,0xac,0x9f,0x0c]
254
255//------------------------------------------------------------------------------
256// Store multiple 1-element structures from three consecutive registers
257// (post-index)
258//------------------------------------------------------------------------------
259         st1 { v0.16b, v1.16b, v2.16b }, [x0], x1
260         st1 { v15.8h, v16.8h, v17.8h }, [x15], x2
261         st1 { v31.4s, v0.4s, v1.4s }, [sp], #48
262         st1 { v0.2d, v1.2d, v2.2d }, [x0], #48
263         st1 { v0.8b, v1.8b, v2.8b }, [x0], x2
264         st1 { v15.4h, v16.4h, v17.4h }, [x15], x3
265         st1 { v31.2s, v0.2s, v1.2s }, [sp], #24
266         st1 { v0.1d, v1.1d, v2.1d }, [x0], #24
267// CHECK: st1 { v0.16b, v1.16b, v2.16b }, [x0], x1
268// CHECK:     // encoding: [0x00,0x60,0x81,0x4c]
269// CHECK: st1 { v15.8h, v16.8h, v17.8h }, [x15], x2
270// CHECK:     // encoding: [0xef,0x65,0x82,0x4c]
271// CHECK: st1 { v31.4s, v0.4s, v1.4s }, [sp], #48
272// CHECK:     // encoding: [0xff,0x6b,0x9f,0x4c]
273// CHECK: st1 { v0.2d, v1.2d, v2.2d }, [x0], #48
274// CHECK:     // encoding: [0x00,0x6c,0x9f,0x4c]
275// CHECK: st1 { v0.8b, v1.8b, v2.8b }, [x0], x2
276// CHECK:     // encoding: [0x00,0x60,0x82,0x0c]
277// CHECK: st1 { v15.4h, v16.4h, v17.4h }, [x15], x3
278// CHECK:     // encoding: [0xef,0x65,0x83,0x0c]
279// CHECK: st1 { v31.2s, v0.2s, v1.2s }, [sp], #24
280// CHECK:     // encoding: [0xff,0x6b,0x9f,0x0c]
281// CHECK: st1 { v0.1d, v1.1d, v2.1d }, [x0], #24
282// CHECK:     // encoding: [0x00,0x6c,0x9f,0x0c]
283
284//------------------------------------------------------------------------------
285// Store multiple 1-element structures from four consecutive registers
286// (post-index)
287//------------------------------------------------------------------------------
288         st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1
289         st1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2
290         st1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64
291         st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64
292         st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
293         st1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4
294         st1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32
295         st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0], #32
296// CHECK: st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1
297// CHECK:     // encoding: [0x00,0x20,0x81,0x4c]
298// CHECK: st1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2
299// CHECK:     // encoding: [0xef,0x25,0x82,0x4c]
300// CHECK: st1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64
301// CHECK:     // encoding: [0xff,0x2b,0x9f,0x4c]
302// CHECK: st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64
303// CHECK:     // encoding: [0x00,0x2c,0x9f,0x4c]
304// CHECK: st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
305// CHECK:     // encoding: [0x00,0x20,0x83,0x0c]
306// CHECK: st1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4
307// CHECK:     // encoding: [0xef,0x25,0x84,0x0c]
308// CHECK: st1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32
309// CHECK:     // encoding: [0xff,0x2b,0x9f,0x0c]
310// CHECK: st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0], #32
311// CHECK:     // encoding: [0x00,0x2c,0x9f,0x0c]
312
313//------------------------------------------------------------------------------
314// Store multiple 2-element structures from two consecutive registers
315// (post-index)
316//------------------------------------------------------------------------------
317         st2 { v0.16b, v1.16b }, [x0], x1
318         st2 { v15.8h, v16.8h }, [x15], x2
319         st2 { v31.4s, v0.4s }, [sp], #32
320         st2 { v0.2d, v1.2d }, [x0], #32
321         st2 { v0.8b, v1.8b }, [x0], x2
322         st2 { v15.4h, v16.4h }, [x15], x3
323         st2 { v31.2s, v0.2s }, [sp], #16
324// CHECK: st2 { v0.16b, v1.16b }, [x0], x1
325// CHECK:     // encoding: [0x00,0x80,0x81,0x4c]
326// CHECK: st2 { v15.8h, v16.8h }, [x15], x2
327// CHECK:     // encoding: [0xef,0x85,0x82,0x4c]
328// CHECK: st2 { v31.4s, v0.4s }, [sp], #32
329// CHECK:     // encoding: [0xff,0x8b,0x9f,0x4c]
330// CHECK: st2 { v0.2d, v1.2d }, [x0], #32
331// CHECK:     // encoding: [0x00,0x8c,0x9f,0x4c]
332// CHECK: st2 { v0.8b, v1.8b }, [x0], x2
333// CHECK:     // encoding: [0x00,0x80,0x82,0x0c]
334// CHECK: st2 { v15.4h, v16.4h }, [x15], x3
335// CHECK:     // encoding: [0xef,0x85,0x83,0x0c]
336// CHECK: st2 { v31.2s, v0.2s }, [sp], #16
337// CHECK:     // encoding: [0xff,0x8b,0x9f,0x0c]
338
339//------------------------------------------------------------------------------
340// Store multiple 3-element structures from three consecutive registers
341// (post-index)
342//------------------------------------------------------------------------------
343         st3 { v0.16b, v1.16b, v2.16b }, [x0], x1
344         st3 { v15.8h, v16.8h, v17.8h }, [x15], x2
345         st3 { v31.4s, v0.4s, v1.4s }, [sp], #48
346         st3 { v0.2d, v1.2d, v2.2d }, [x0], #48
347         st3 { v0.8b, v1.8b, v2.8b }, [x0], x2
348         st3 { v15.4h, v16.4h, v17.4h }, [x15], x3
349         st3 { v31.2s, v0.2s, v1.2s }, [sp], #24
350// CHECK: st3 { v0.16b, v1.16b, v2.16b }, [x0], x1
351// CHECK:     // encoding: [0x00,0x40,0x81,0x4c]
352// CHECK: st3 { v15.8h, v16.8h, v17.8h }, [x15], x2
353// CHECK:     // encoding: [0xef,0x45,0x82,0x4c]
354// CHECK: st3 { v31.4s, v0.4s, v1.4s }, [sp], #48
355// CHECK:     // encoding: [0xff,0x4b,0x9f,0x4c]
356// CHECK: st3 { v0.2d, v1.2d, v2.2d }, [x0], #48
357// CHECK:     // encoding: [0x00,0x4c,0x9f,0x4c]
358// CHECK: st3 { v0.8b, v1.8b, v2.8b }, [x0], x2
359// CHECK:     // encoding: [0x00,0x40,0x82,0x0c]
360// CHECK: st3 { v15.4h, v16.4h, v17.4h }, [x15], x3
361// CHECK:     // encoding: [0xef,0x45,0x83,0x0c]
362// CHECK: st3 { v31.2s, v0.2s, v1.2s }, [sp], #24
363// CHECK:     // encoding: [0xff,0x4b,0x9f,0x0c]
364
365//------------------------------------------------------------------------------
366// Store multiple 4-element structures from four consecutive registers
367// (post-index)
368//------------------------------------------------------------------------------
369         st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1
370         st4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2
371         st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64
372         st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64
373         st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
374         st4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4
375         st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32
376// CHECK: st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1
377// CHECK:     // encoding: [0x00,0x00,0x81,0x4c]
378// CHECK: st4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2
379// CHECK:     // encoding: [0xef,0x05,0x82,0x4c]
380// CHECK: st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64
381// CHECK:     // encoding: [0xff,0x0b,0x9f,0x4c]
382// CHECK: st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64
383// CHECK:     // encoding: [0x00,0x0c,0x9f,0x4c]
384// CHECK: st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
385// CHECK:     // encoding: [0x00,0x00,0x83,0x0c]
386// CHECK: st4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4
387// CHECK:     // encoding: [0xef,0x05,0x84,0x0c]
388// CHECK: st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32
389// CHECK:     // encoding: [0xff,0x0b,0x9f,0x0c]
390